Method and program product for protecting information in EDA...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07437698

ABSTRACT:
Sensitive circuit design information in HDL Interface Logic Models such as module names and structures within certain EDA tool design views is eliminated by substituting selected instance and net names with unrelated unique identifiers prior to transferring the design views as part of a simulation model of a circuit design, and consequently avoiding unauthorized use of that information. The method for encoding signal names in different design views of an IC design includes providing a list of names contained in a plurality of design databases, changing each name in the list of names to a protected name, and substituting each changed name with an associated protected name in each design view database.

REFERENCES:
patent: 5937190 (1999-08-01), Gregory et al.
patent: 6263483 (2001-07-01), Dupenloup
patent: 6886140 (2005-04-01), Regnier
patent: 7168041 (2007-01-01), Durrill et al.
patent: 2003/0004699 (2003-01-01), Choi et al.
patent: 2005/0229128 (2005-10-01), Sripada
patent: 2007/0050745 (2007-03-01), Dinter et al.

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