Method and program product for avoiding cache congestion by...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring

Reexamination Certificate

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Reexamination Certificate

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10694302

ABSTRACT:
A method of allocating memory operates to avoid overlapping hot spots in cache that can ordinarily cause cache thrashing. This method includes steps of determining a spacer size, reserving a spacer block of memory from a memory pool, and allocating memory at a location following the spacer block. In an alternative embodiment, the spacer size is determined randomly in a range of allowable spacer size. In other alternative embodiments, spacers are allocated based upon size of a previously allocated memory block.

REFERENCES:
patent: 5675790 (1997-10-01), Walls
patent: 5930827 (1999-07-01), Sturges
patent: 6804761 (2004-10-01), Chen et al.
patent: 6957294 (2005-10-01), Saunders et al.
Chavarria-Miranda, Daniel and John Mellor-Crummey, “An Evaluation of Data-Parallel Compiler Support for Line-Sweep Applications”. Apr. 2003, Journal of Instruction-Level Parallelism 5, pp. 17-28.
Cray T3ETM Fortran Optimization Guide—004-2518-002, “Chapter 4. Single-PE Optimization—Section 4.3: Optimization for Cache”, Jan. 1999, Sections 4.3.0-4.3.3.
Chavarria-Miranda, Daniel and John Mellor-Crummey, “An Evaluation of Data-Parallel Compiler Support for Line-Sweep Applications”. Apr. 2003, Journal of Instruction-Level Parallelism 5, pp. 1-29.

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