Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-11-23
2002-09-03
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S635000, C438S634000
Reexamination Certificate
active
06444564
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a method for forming interconnect lines with improved use of low k dielectric material in the intermetal dielectric material electrically separating such interconnect lines.
2. Description of the Related Art
An integrated circuit includes numerous active devices arranged on a single substrate. In order to implement desired functions, select components of a circuit must be interconnected. Interconnects, or thin lines of conductive material, are used to form electrical connections between active devices. In the desire to build more complex integrated circuits, the active device density within a given chip has greatly increased. Because of space limitations caused in large part by the increase in active device density, multiple levels of interconnect must often be used. Within each level of interconnect, interconnect lines are insulated from underlying levels, overlying levels, and each other by dielectric materials.
The performance of an integrated circuit is limited by its propagation delay, notably known as the time required for a signal to travel from one point within the circuit to another. As the feature size decreases, the need to reduce the resistance and capacitance, and thus the RC delay, associated with interconnection paths becomes more urgent. For example, in submicron metal oxide semiconductor field-effect transistors (MOSFETs) the interconnect RC delay can exceed delays due to gate switching. In order to continue to improve integrated circuit performance, these RC delays must be decreased.
There are numerous factors that effect the RC delay of interconnect lines. One of these factors is the resistance, R, of the interconnect lines, which may be defined as:
R
=(&rgr;
L
)/
W
L
T
C
where &rgr; represents resistivity of the conductive material, L is the interconnect length, W
L
is the interconnect width, and T
C
is the interconnect thickness. Obviously, if low resistivity materials are used as interconnect, signals will be able to propagate through the circuit faster. Consequently, metals such as aluminum and copper are often used to form interconnect lines. Although increasing the width and thickness of interconnect lines will also help to decrease the resistivity of such lines, increases in line dimensions are limited by the available space and the fact that the capacitance between lines increases as the spacing between lines decreases.
Interconnect RC delay is also affected by the parasitic capacitances between laterally spaced conductors (i.e., intralevel capacitance) and between vertically spaced conductors or between a conductor and the underlying substrate (i.e., interlevel capacitance). Increases in active device density may cause the dielectric spacing between levels of interconnect and within levels of interconnect to decrease. As the dielectric spacing between levels of interconnect decreases, the interlevel capacitance must conversely increase. Likewise, as the dielectric spacing within a level of interconnect decreases, the intralevel capacitance increases. Unfortunately, increases in these parasitic capacitances may result in lengthening of the propagation delay.
Interlevel and intralevel capacitances may be reduced, however, by reducing the permittivity, ∈, of the intermetal dielectric material used to separate conductors. By normalizing the permittivity, ∈, of a material to the permittivity of vacuum, ∈
o
, the relative permittivity of a material can be determined. Relative permittivity, or dielectric constant, k, is typically used in place of permittivity. The dielectric constant of a material is defined as:
k
=∈/∈
o
The k value of the dielectric material used to insulate interconnect lines has a strong effect on the intermetal capacitance, C, which may be defined as follows:
C=k∈
o
W
L
T
C
/T
d
where T
d
is the thickness of the dielectric material between adjacent interconnect lines. Not only will low k dielectric materials (i.e., those materials that have k values less than about 3.5) reduce intermetal parasitic capacitances, but many, such as low k spin-on glasses (“SOGs”) may be used to fill narrower spaces without causing voids often encountered in conventional chemical vapor deposited (“CVD”) films. Common SOG materials include silicates or siloxanes mixed in alcohol-based solvents.
Because of the aforementioned properties, SOGs are often used as intermetal dielectrics. A conventional process that incorporates SOG in this manner is the etchback SOG process. One unfortunate characteristic of SOGs (and many other low k dielectric materials) is that they have a low density, and thus tend to absorb moisture easily. If contacts are formed through SOG, moisture from the SOG may migrate into the vias, potentially causing the undesirable “poisoned via” effect. An advantage of the etchback SOG process is that SOG is removed from raised areas where contacts may be formed.
In this process, a first interlevel dielectric film is CVD deposited over a set of patterned metal interconnect and serves as a liner between the metal and any dielectric material deposited in the gaps between adjacent interconnect. This film, usually a CVD silicon oxide (“oxide”), will generally conform to the interconnect topography. As a result, the spaces between adjacent interconnect will be more narrow than before the interlevel dielectric was deposited. A SOG film is then spun on, and fills the remainder of the gap between the interconnects. Portions of the SOG layer and the uppermost layer of the first CVD dielectric layer are then removed, typically using a dry plasma etch process. In this manner, SOG material is removed in areas where vias will be etched and contacts formed, but remains in the gaps between interconnect. A second oxide interlevel dielectric film is then deposited.
One problem of the etchback SOG process is that the first interlevel dielectric must be deposited at a thickness sufficient to prevent the underlying metal interconnects from being exposed during the etchback step. Because this film is deposited at this thickness over the entire interconnect topography, the amount of space available between adjacent interconnect for low k dielectric material may be reduced. If the interlevel dielectric layer becomes too thick, the spacing may even be reduced to the point where SOG cannot sufficiently flow between the coated interconnect. As the spacing between adjacent interconnects grows smaller, this “pinching off” effect only increases.
In addition, there is typically a substantial difference in the etch rate between the SOG in the gap fill and the oxide in the interlevel dielectric layer. As a result, the topography defined by the interlevel dielectric film and the SOG gap fill may not be sufficiently planar. An insufficient degree of non-planarization can hinder the reliable manufacture of overlying interconnects. The need for an increased degree of planarization becomes even greater as the interconnect pitch (i.e., the sum of the interconnect line width and the space between the adjacent interconnect lines) decreases. Furthermore, the etch chemistry of many low dielectric constant materials closely resembles that of photoresist, which makes them very difficult to etch. Consequently, it is troublesome to incorporate such materials into process flows that incorporate etchback techniques in a manner similar to the SOG etchback process.
Therefore, it would be desirable to develop a technique for fabricating interconnect in which the amount of low k dielectric material utilized could be increased. It would also be advantageous to increase the degree of planarization of the intermetal dielectric topography. The improved process would allow the use of difficult-to-etch, low k value dielectric materials.
SUMMARY OF THE INVENTION
The problems identified above are in large part solved by the method presented herein for forming interconnect lines with improved use of low k dielectric
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Everhart Caridad
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