Method and processing unit for selective value prediction...

Electrical computers and digital processing systems: processing – Processing control – Branching

Reexamination Certificate

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C712S225000

Reexamination Certificate

active

10484195

ABSTRACT:
The present invention relates to a processing unit for executing instructions in a computer system and to a method in such a processing unit. According to the present invention a decision is made whether or not to base execution on a value prediction (P), wherein the decision is based on information associated with the estimated time gain of execution based on a correct prediction. According to an embodiment of the present invention the decision regarding whether or not to execute speculatively is based on information regarding whether a cache hit or a cache miss is detected in connection with a load instruction. In an alternative embodiment of the present invention the decision is based on information regarding the dependency depth of the load instruction, i.e. the number of instructions that are dependent on the load.

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patent: 5996060 (1999-11-01), Mendelson et al.
patent: 6487639 (2002-11-01), Lipasti
patent: WO 93/18459 (1995-06-01), None
patent: WO 98/21684 (1998-05-01), None
patent: WO 00/34882 (2000-06-01), None
Brad Calder, Genn Reinman and Dean M. Tullsen; “Selective Value Prediction”; 1999.
Diefendorff, “PC Processor Microarchitecture.”, Microdesign Resources, Jul. 12, 1999, pp. 16-22.
Lipasti et al., “Value Locality and Load Value Prediction”, ASPLOS VII, Oct. 1996, pp. 136-147.
Tune et al., Dynamic Prediction of Critical Path Instructions, in the Proceedings of the 7thInternational Symposium on High Performance Computer Architecture, Jan. 2001, pp. 1-11.
Reinman et al., Predictive Techniques for Aggressive Load Speculation, Published in the Proceedings of The Annual 31stInternational Symposium on Microarchitecture, Dec. 1998 pp. 1-11.
Calder et al., “Selective Value Prediction”, Published in the Proceedings of the 26thInternational Symposium on Computer Architecture, May 1999, pp. 111.
ABSTRACT, JP-7105092, Naoyuki et al., filed Sep. 30, 1993.

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