Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-02
2007-10-02
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
11267569
ABSTRACT:
The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.
REFERENCES:
patent: 4931946 (1990-06-01), Ravindra et al.
patent: 6401230 (2002-06-01), Ahanessians et al.
patent: 6493855 (2002-12-01), Weiss et al.
patent: 7069523 (2006-06-01), Nation et al.
patent: 2004/0117744 (2004-06-01), Nation et al.
patent: 2005/0097499 (2005-05-01), Sun et al.
Pileggi, et al., “Exploring Regular Fabrics to Optimize the Performance-Cost Trade Off”, working white paper for Carnegie Mellon University, Dpt. of Electrical and Computer Engineering,DAC 2003, Jun. 2-6, 2003, (6 pages).
Pileggi, et al., Exploring regular fabrics to optimize the performance-cost trade-off, DAC (Anaheim, California), (Jun. 2-6, 2003).
Lanza Lucio L.
Pileggi Lawrence T.
Strojwas Andrzej J.
Dimyan Magid Y.
PDF Solutions, Inc.
Whitmore Stacy A.
LandOfFree
Method and process for design of integrated circuits using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and process for design of integrated circuits using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and process for design of integrated circuits using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3827315