Method and planarizing polysilicon layer

Details Method and planarizing polysilicon layer Method and planarizing polysilicon layer

1999-03-29

2001-08-21

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S669000, C438S672000, C438S684000, C438S719000, C438S764000

Reexamination Certificate

active

06277741

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method for planarizing a polysilicon layer.
2. Description of the Related Art
One of the conventional methods for planarizing a polysilicon layer is chemical-mechanical polishing. In order to obtain a planarized polysilicon layer, it is necessary to deposit a thick polysilicon layer. Planarization of the thick polysilicon layer is not affected by the topography of an underlying layer. However, if the thickness of the polysilicon layer increases, it requires a longer etching time to obtain a desired thickness and degree of planarization of the polysilicon layer. This, in turn, causes the fabrication costs to increase. The reliability of devices may be degraded, as well.
SUMMARY OF THE INVENTION
The invention provides a method for planarizing a polysilicon layer. A polysilicon layer is etched by isotropic dry etching. The isotropic dry etching is performed with an oxygen-based gas and a halogen-based gas.
In addition, the invention provides a method of fabricating a landing pad. A substrate comprising a metal oxide semiconductor transistor is provided. A cap layer is formed on a gate electrode of the metal oxide semiconductor transistor. A polysilicon layer is formed over the substrate. An isotropic dry etching step is performed to planarize the polysilicon layer. The polysilicon layer is patterned to form a landing pad on a source/drain region of the metal oxide semiconductor transistor. The polysilicon layer is etched by isotropic dry etching with an oxygen-based gas and a halogen-based gas.
In the isotropic dry etching, the oxygen-based gas comprises an nitrogen oxide and oxygen gas. The nitrogen oxide gas includes NO, NO
2
, N
2
O, or the combination thereof. The halogen-based gas includes F, Cl, Br, I, NF
3
, SF
6
, Cl
2
, HCl, SiCl
4
, fluorocarbon, or the combination thereof. The fluorocarbon includes CF
4
, CHF
3
, CH
2
F
2
, and CH
3
F.
In comparison with a conventional method, which uses chemical-mechanical polishing, the present invention forms a planarized polysilicon layer by dry isotropic etching. A thick polysilicon layer, as seen in the conventional method, is unnecessary. Thus, the fabrication cost of the present invention is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5338398 (1994-08-01), Szwejkowski et al.
patent: 5340774 (1994-08-01), Yen
patent: 5381046 (1995-01-01), Cederbaum et al.
patent: 5895961 (1999-04-01), Chen
patent: 5976977 (1999-11-01), Hong
patent: 6100138 (2000-08-01), Tu

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