Method and memory system in which operating mode is set...

Details Method and memory system in which operating mode is set... Method and memory system in which operating mode is set...

2006-05-09

2006-05-09

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060, C365S201000

Reexamination Certificate

active

07042800

ABSTRACT:
A memory system, memory device, and method for setting an operating mode of a memory device include a memory cell array; row and column decoders which select a row and a column of the memory cell array, respectively, according to a multi-bit address signal; and a mode control circuit which receives at least one bit from the multi-bit address signal used in the selection of the row or the column, and which sets an operating mode of the memory device according to the at least one bit, wherein the operating mode is one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.

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128M bits Self Terminated Interface DDR SDRAM, ELIPIDA, Nov. 2002, Document No. E0288E20 (Ver. 2.0), pp. 1-46.

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