Method and mechanism to use a cache to translate from a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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Reexamination Certificate

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07032074

ABSTRACT:
A multi-processor computer architecture reduces processing time and bus bandwidth during snoop processing. The architecture includes processors and local caches. Each local cache corresponds to one of the processors. The architecture includes one or more virtual busses coupled to the local caches and the processors, and one or more intermediary caches, where at least one intermediary cache is coupled to each virtual bus. Each intermediary cache includes a memory array and means for ensuring the intermediary cache is inclusive of associated local caches. The architecture further includes a main memory having a plurality of memory lines accessible by the processors.

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patent: 6473835 (2002-10-01), Luick
Motorola, “MC 88410 Secondary Cache Controller User's Manual”, 1992, P 2-41 to 2-43.
Handy, “The Cache Memory Book”, 1993, P 250.

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