Method and mechanism for performing improved timing analysis...

Details Method and mechanism for performing improved timing analysis... Method and mechanism for performing improved timing analysis...

2002-06-14

2004-07-06

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06760894

ABSTRACT:

FIELD OF THE INVENTION
The field of the present invention relates to electronic design automation and, more particularly, to methods and mechanisms for performing improved timing analysis upon electronic circuit blocks.
BACKGROUND AND SUMMARY OF THE INVENTION
Advances in silicon technology increasingly allow larger and more complex designs to be formed on a single chip. Designs may consist of millions or tens of millions of transistors on a single chip. At the same time, however, market demands continue to push designers to develop designs more rapidly and efficiently. A recent trend to increase design speed and efficiency involves the re-use or recycling of electronic circuit models of circuit blocks (which may have one or more subsystems), which are commonly referred to as “cores” or “IPs” (for “Intellectual Properties”). Once the design for a circuit block has been tested and verified, it can be re-used in other applications which may be completely distinct from the application which led to its original creation. For example, a subsystem for a cellular phone ASIC may contain a micro-controller as well as a digital signal processor and other components. After the design for the cellular phone subsystem has been tested and verified, the circuit block could be re-used in, for example, an automotive application. Design reuse of circuit blocks allows a designer to complete a design much faster than building the entire design from scratch, and avoids the need for debugging, testing and verification of the subsystems embodied circuit block. Circuit blocks may be of various sizes and levels of complexity, and one circuit block may comprise one or more subsystems, where each subsystem is itself a circuit block. A virtual component block shall be used herein to refer to any model or abstract representation of a circuit block.
Timing models may be used to characterize the timing of a circuit block without having access to the actual circuit block once the timing model is constructed. While timing models have been found to be convenient for expediting and simplifying the circuit design process, the successful use of timing models hinges on the ability to accurately characterize their timing and functionality. In analyzing large circuits, it is often necessary to sacrifice some accuracy given the computational complexity involved, e.g., some methods of timing analysis performed on circuits consider false paths. False paths are signal paths that are never sensitized, i.e., activated, in actual operation. While it may be possible to detect false paths, identifying and removing them when undergoing timing analysis on large circuits is much too slow to be of practical value.
A number of techniques have been developed or proposed for performing timing estimation analyses on circuit blocks, including static timing analysis and functional timing analysis. Static timing analysis involves the calculation of a worst-case structural (or topological) delay between a circuit block's input and an output, but ignores the functionality of the circuit block. Static timing analysis methods make no attempt to detect false paths.
Functional timing analysis methods attempt to rely on the fact that the delays in a circuit block are linked to the way a circuit functions. “Functionality” in this context refers to the logical value computed for each node in the circuit block (“circuit node”), given an input vector. Unlike traditional static timing analysis, functional timing analysis uses a circuit block's function as well as its structure to characterize delays and timing constraints.
Two widely used methods for functional timing analysis are symbolic analysis via binary-decision diagrams (BDDs), and boolean search methodologies that systematically enumerate the input space. Both methods assume that the delays of a circuit block depend on the values of all of its inputs. These methods aim at finding an input vector that sensitizes the true longest path. However, they both have the disadvantage that their complexity increases exponentially with circuit size, limiting their applicability, or requiring unacceptably large amounts of computation resources for larger circuit designs.
A more practical approach is to assume that a circuit block's delay depend on only a subset of its inputs. This is typical of datapath circuits, where a small number of control inputs determine the delays between a large number of data inputs and data outputs. A simple example is shown by a circuit
50
in
FIG. 1
, wherein the control inputs
60
to a large extent determine the delays between the data inputs
55
and the data outputs
70
. For example, if the control inputs
60
sensitize the signal path to enable operation
1
, then a delay of 10 is observed, while only a delay of 2 is observed if operation
3
is performed.
Methods of timing analysis have been developed based upon the recognition that the control inputs play a role in determining the delays between the data inputs and outputs. These methods generally trade accuracy for computation efficiency. For example, some static timing analyzers employ a systematic case analysis capability whereby the user sets some inputs to constant values prior to performing the timing analysis. A drawback with such timing analysis methods is that they suffer from delay underestimation. Delay underestimation is a serious problem in circuit design because it can lead to incorrect operation.
One timing analysis benchmark involves calculation of the delay in a so-called “floating mode” of operation. In a floating mode of operation, each circuit node initially has an unknown value. Upon the application of an input vector to the circuit, the circuit node undergoes a series of transitions or events before it eventually stabilizes at a value determined by the circuit's internal static functionality.
Examples of event propagation using principles of “controlling” and “non-controlling” values are illustrated in
FIGS. 2A and 2B
, for the simple case of a two-input AND gate. A controlling value (CV) at a gate input is one that determines the output of the gate regardless of the values of the other inputs. A non-controlling value (NCV) does not change the gate output by itself. For an AND gate, the controlling and non-controlling values are 0 and 1, respectively. The arrival time of a gate output is determined by the earliest input with a controlling value, if it exists; otherwise, the latest input with the non-controlling value determines the output arrival time. In
FIG. 2A
, input “a” is a controlling value because it will eventually become 0, whereas in
FIG. 2B
, neither input “a” nor “b” is a controlling value because both will stay at 1. Because, input “a” has a controlling value in
FIG. 2A
, the gate output arrival time “T
z
” is determined only by the arrival time T
a
of input “a”, plus the gate delay d. In
FIG. 2B
, however, because neither input “a” nor “b” has a controlling value, the output arrival time T
z
is given by the latest input arrival time (in this example, T
b
) plus the gate delay d. Because the last arriving event at any node determines the delay up to that node, the terms “arrival time” and “delay” are used interchangeably herein.
For a generic gate having inputs “a” and “b” and output “z” in floating mode (FM), these concepts may be shown in the form of a truth table, T
z
FM
, such as appearing in Table 1 below.
TABLE 1
v
a
v
b
T
z
FM
CV
CV
min(T
a
,T
b
) + d
CV
NCV
T
a
+ d
NCV
CV
T
b
+ d
NCV
NCV
max(T
a
,T
b
) + d
It is possible to write a logical expression (or predicate) that describes whether an input event propagates from a gate input to the gate output; such expressions are sometimes referred to as “sensitization conditions” or “propagation conditions.” Referring back to
FIGS. 2A and 2B
, the sensitization condition for the path from input “a” to gate output “z” may be denoted COND
az
. In
FIG. 2A
, analyzing the path of the gate using floating mode propagation condition, the path is “sensitized,” so COND
az
is 1 (true).

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