Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-09-15
2008-08-26
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C430S005000, C430S030000
Reexamination Certificate
active
07418682
ABSTRACT:
A method and mechanism is disclosed for performing a spacing rule DRC check that does not require an excessive number of passes through the IC design. In one approach, a two-pass approach is employed to perform a spacing check. In an approach, a polygons are associated with a family of related polygons.
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Cadence Design Sysyems, Inc.
Chiang Jack
Doan Nghia M
Vista IP Law Group LLP
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