Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2006-01-17
2006-01-17
Browne, Lynne H. (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S501000, C713S502000, C713S601000, C327S291000, C327S156000, C377S078000, C377S080000
Reexamination Certificate
active
06988217
ABSTRACT:
A method and mechanism for generating a clock signal with a relatively linear increase or decrease in clock frequency. A first clock signal is generated with a first frequency which is then used to generate a second clock signal with a second frequency. The second frequency is generated by dropping selected pulses of the first clock signal. Particular patterns of bits are stored in a storage element. Bits are then selected and conveyed from the storage element at a frequency determined by the first clock signal. The conveyed bits are used to construct the second clock signal. By selecting the particular pattern of bits selected and conveyed, the frequency of the second clock signal may be determined. Further, by changing the patterns of bits within the registers at selected times, the frequency of the second clock signal may be made to change in a relatively linear manner.
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International Search Report, Application No. PCT/US 02/41658, mailed May 14, 2004.
Madrid Philip E.
Meyer Derrick R.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Patel Nitin C.
Rankin Rory D.
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