Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1997-09-25
2000-08-29
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711112, 711111, 711113, 360 48, G06F 1200
Patent
active
061122777
ABSTRACT:
A staging method and means for both device read and update write operations in which messages and commands between a storage subsystem and a fixed-block formatted RAID array emulating a variable-length record (CKD) formatted device for both read and write operations are evaluated to ascertain whether the record addressing was random and truly in record mode. If they are in that mode, then partial track staging by the RAID array control from the fixed-block formatted HDDs to a subsystem cache or the like would reduce device contention by reading and staging less than full track.
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DFSMS/MVS, Remote Copy Administrator's Guide and Reference, IBM , 1996.
Bui Thao B.
Chen James C.
Ng Chan Y.
Bataille Pierre-Michel
Cabeca John W.
International Business Machines - Corporation
Klein Esther E.
Raissinia Abdy
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