Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2000-09-22
2002-08-06
Yoo, Do Hyun (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S150000, C711S141000, C707S793000, C707S793000
Reexamination Certificate
active
06430659
ABSTRACT:
1. BACKGROUND OF THE INVENTION
1.1 Field of the Invention
The present invention relates to means and a method of administrating in a computer system global data elements shared by a multitude of exploiters. More particularly the means and the method of the present invention address said administration of global data elements within the context of multiprocessor computer systems.
1.2 Description and Disadvantages of Prior Art
A well-known area within computer system technology wherein global data elements shared by a multitude of exploiters are faced with the problem of contention among the exploiters for the global data elements is the area of multiprocessor computer systems. Contention among the processors to access a specific memory address is a common performance bottleneck on these multiprocessor computers.
State of the art processors have on-chip caches, where copies of the most frequently accessed memory addresses are stored. These caches are small and can only store a small subset of the entire system memory addresses. An item in the cache can be accessed more quickly than an item in memory, since the cached item is already on the chip, and the actual item must be first fetched over the memory bus of the system. An access which can be serviced from the cache is known as a “hit”, otherwise it is a “miss”. The time difference between a hit and a miss is measured as the extra CPU cycles required for the access instruction to complete, and is called the “miss penalty”. Miss penalties vary for different processors, but are quite significant. On a typical processor, a cache hit for a four byte word may complete in four cycles, but a miss may require an additional twelve cycles. This means that a load from memory is four times longer than one from cache. Thus, the importance and impact of processor caches on system performance is obvious.
However, the effectiveness of processor caches is degraded on multiprocessor systems, when all the processors attempt to access a specific memory address at the same time. When this occurs, “contention” for the memory address is said to exist. A processor may only use the copy of the memory address in its cache, when it has not been modified by another processor since it was loaded into the cache. If the address has been modified by another processor, the value in the cache is said to be “invalid”. Invalid cache entries may not be used by a processor, and instead the valid address must be fetched over the memory bus, an operation that requires many more CPU cycles. Thus, in a worst case scenario, when all processors are constantly modifying the same address, the cache entries are never valid, and the cache itself is entirely useless. The system performance is reduced to that of one with no processor caches at all.
This problem of contention commonly occurs for instance with global variables used to manage system resources and as statistic counters or other global variables with a frequent update pattern. A solution currently used by software designers to solve this problem is to replace the global variables with per-CPU variables; i.e. to replace the global variables by local variables dedicated to a specific exploiter. For example, a single memory management pool for the entire system can be replaced by many pools, each of which is only used by a specific CPU. Since the variables for each pool are only used by the specific CPU, contention among the various processors never occurs, since each CPU only uses the variables in the pool assigned to it. This can also be used for certain statistic counters: a single global counter can be replaced with a set of per-CPU counters. Since contention never exists, the cache entries remain valid, and the performance gains of the processor caches remain effective.
However, this approach of assigning variables and resources to specific CPUs, or in general to specific exploiters only, is not always feasible. There are always cases where global variables are required, for instance, to hold system wide, i.e. global values, which cannot be split.
Thus, there is a need in the state of art for further improvement.
1.3 Objective of the Invention
The invention is based on the objective to provide a technology for administrating in a computer system global data elements shared by a multitude of exploiters to reduce contention among the exploiters for the global data elements and to improve performance of the computer system.
It is a further objective to provide this technology within the context of multiprocessor computer systems.
2. SUMMARY AND ADVANTAGES OF THE INVENTION
The objectives of the invention are solved by the independent claims. Further advantageous arrangements and embodiments of the invention are set forth in the respective sub claims.
The present invention relates to means, a method and a computer program product of administrating in a computer system a global data element shared by a multitude of exploiters within said computer system for reducing contention among said exploiters.
It is suggested to execute a first step by a first exploiter of accumulating one or a multitude of modifications performed by said first exploiter with respect to the current contents of said global data element into a first local data element not shared by other exploiters.
In a second step executed by the first exploiter a size of the accumulated modifications in the first local data element with respect to the current contents of the global data element is determined. Moreover it is determined, if said size exceeds a specified quantum.
If said size exceeds the specified quantum, the global data element is updated with the accumulated modifications as new contents.
Contention situations are caused by update operations of the global data element. The invention reduces the probability of a contention occurring for every modification, since the individual modifications (which used to cause contentions) are accumulated within a local data element, and only the accumulated modification to the global data element (which now occurs less often) can cause a contention. This results in a significant reduction of the contention, which directly translates to an increased overall system performance.
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Cossmann Helmut
Dierks Herman
Hymas William James
Sharma Satya
McLean Kimberly
Yoo Do Hyun
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