Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
2000-05-19
2004-03-30
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S010000, C710S015000, C710S018000, C710S052000, C710S038000, C710S056000, C710S111000, C709S241000, C709S232000
Reexamination Certificate
active
06714997
ABSTRACT:
FIELD OF INVENTION
The subject of the present invention in general pertains to a new processor instruction, using a new input/output (I/O) interface, called queued-direct I/O (QDIO), between a program and a new integrated communications adapter.
BACKGROUND OF THE INVENTION
In a network computing environment, multitudes of commands and requests for retrieval and storage of data are processed every second. To properly address the complexity of routing these commands and requests, environments with servers have traditionally offered integrated network connectivity to allow direct attachments of clients such as Local Area Networks (LANs). Given the size of most servers, the number of clients usually is in the range of hundreds to thousands and the bandwidth required in the 10-100 Mbits/sec range. However, in recent years the servers have grown and the amount of data they are required to handle has grown with them. As a result, the existing I/O architectures need to be modified to support this order of magnitude increase in the bandwidth.
In addition, new Internet applications have increased the demand for improved latency. The adapters must support a larger number of users and connections to consolidate the network interfaces which are visible externally. The combination of all the above requirements presents a unique challenge to server I/O subsystems.
Furthermore, in large environments such as International Business Machines Enterprise System Architecture/390 (Enterprise System Architecture/390 is a registered trademark of International Business Machines Corporation), there are additional requirements that the I/O subsystem must remain consistent with existing support. Applications must continue to run unmodified, and error recovery and dynamic configuration must be preserved or even improved. Sharing of I/O resources must be enabled as well as the integrity of the data being sent or received. This presents new and complex challenges that need to be resolved.
In order to achieve bandwidths which are dramatically higher and still achieve other required challenges, a new system architecture is needed.
SUMMARY OF THE INVENTION
In a network computing system having a main storage capable of connecting to at least one application server and an interface element with at least one adapter and a plurality of subchannels, said system being capable of establishing processing communication with at least one application user(s), method and means for an enhanced interpretive instruction execution is provided. First it is determined if a second level of interpretive execution is needed by assessing whether said computing system contains one or more logically partitioned environments, or if the computing system contains an hypervisor environment created within another hypervisor environment.
Second an I-bit is created in the subchannels for controlling the interpretive execution of I/O instructions and allowing said bit to indicate that selected I/O instructions are to be intrepretively executed when a second level of hypervisor is not present. Also a new bit is created within the interpretive-execution state description. Then a mechanism is defined and designed for controlling second level interpretation of the new Signal Adapter (SIGA) Instruction. Signal interception of all I/O instructions is made for the case, when the second level is not present, when both the I-bit for the applicable subchannel and the new bit in said system are set to zero, but the mechanism prohibits interception, allowing for interpretive execution of SIGA, when either the I-bit or the new bit has a value of one.
In the case when a second level of interpretive instruction execution is detected, the mechanism requires interception when either the new bit in the second-level state description is zero, or when both the I-bit for the applicable subchannel and the new bit are zero in the first-level state description. Also in a second level of interpretive instruction execution, the mechanism prohibits interception and allows for interpretive execution of commands when the new bit in the second-level state description is one and either the I-bit for the subchannel or the new bit contains a value of one in the first-level state description.
REFERENCES:
patent: 5265240 (1993-11-01), Galbraith et al.
patent: 5504928 (1996-04-01), Cook et al.
patent: 5555414 (1996-09-01), Hough et al.
patent: 5983310 (1999-11-01), Adams
patent: 6438671 (2002-08-01), Doing et al.
Brice, Jr. Frank W.
Easton Janet R.
Messinger Steven
Tarcza Richard P.
Wyman Leslie W.
Gaffin Jeffrey
Gonzales Floyd A.
International Business Machines - Corporation
Neff Lily
Perveen Rehana
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