Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2003-02-28
2004-08-17
Cuneo, Kamano (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S765010
Reexamination Certificate
active
06777924
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the semiconductor technology and semiconductor processing field. More specifically, the present invention relates to a method for testing a plurality of semiconductor devices on a programmable testing device by means of magazine devices. The testing device has at least one testing location with a plurality of electrical contact devices as a testing location interface and each magazine device has a magazine shaft with a first magazine interface, forming the counterpart to the testing location interface, and also a plurality of second magazine interfaces for the contacting of a semiconductor device in each case. In the generic method,
a plurality of semiconductor devices are arranged one above the other in the magazine shaft;
the magazine shaft is mechanically fastened on the testing location and contacted; and
subsequently, the semiconductor devices in the magazine shaft are simultaneously tested.
In addition, the present invention relates to magazine devices which render such a method possible.
At present, the costs for testing semiconductor devices form a significant part of the overall production costs. In the case of semiconductor memory devices, such as 128 Mb DRAMs (dynamic random access memories), the proportion of production costs made up by testing costs is approximately 15% to 20%.
The testing of semiconductor devices (hereafter also test pieces) generally takes place on programmable testing devices (component testers). If a high throughput of test pieces is required, the testing devices are operated in conjunction with automatic placement machines (handlers).
The automatic placement machine removes the test pieces from a storage device and places them on one of generally a number of testing locations of the testing device. At the testing location, the test piece is mechanically fixed. The fixing by the automatic placement machine in this case takes place for instance by pressure being applied or by a fastening interface to be closed and opened by the automatic placement machine.
The mechanical fixing at the same time ensures an electrically conducting connection between each contact device of the test piece on the one hand and a respectively corresponding contact device of the testing location on the other hand.
Usually, a plurality of testing locations are mechanically combined to form a test board. While a first test board is being loaded with test pieces by the automatic placement machine, the test pieces are being simultaneously tested in parallel with this on the testing device, on an already loaded, second test board.
Since the testing time per semiconductor device is fixed essentially by the functionality of the semiconductor device, the testing costs can be lowered only by a higher throughput of test pieces on the testing device. For this purpose, it is endeavored to reduce further the number of setting-up and loading times on the testing device and increase the number of test pieces tested in parallel.
To lower the testing costs of complex semiconductor devices which have an internal self-testing device (BIST), the commonly assigned, copending application Ser. No. 10/272,344, filed Oct. 15, 2002 therefore describes a magazine device (hereafter magazine) with which a plurality of complex semiconductor devices are simultaneously fixed and contacted at a testing location of a testing device. The internal self-testing device of the semiconductor devices compresses the test result for the tested semiconductor device and outputs the compressed result on a data line in each case (test port) of the test piece.
This allows both the address lines and the control lines of a plurality of semiconductor devices arranged in the magazine to be led while connected to one another to one output port of the testing location in each case. By contrast, the data lines (test ports) at which the test reactions of the test piece are output are respectively led separately to an input port of their own in each case of the testing location. Consequently, a simultaneous stimulation of the test pieces in the magazine takes place via the parallel-connected address and control lines and an essentially simultaneous, compressed fault output takes place on separate data lines.
The parallelism of the testing operation is increased by a factor corresponding to the number of test pieces per magazine.
Faulty contacts between the test piece and the testing device during the testing operation make up a further contribution to the testing costs. One reason for faulty contacts is the wearing of the contact devices of the testing device caused by the high throughput on the testing device and another is the configuration of the contact devices of the test pieces. The latter are generally intended to be soldered in later and are designed correspondingly. On the other hand, the contact devices of the test piece are only pressed during the testing on the testing device.
If, instead of the test piece, a magazine with contact devices which are not intended to be soldered in later is contacted at the test location, these contact devices can be designed for optimum and low-wearing operation in conjunction with the testing location.
In addition, the filling of the magazine and a simple test of the contacting of the semiconductor devices takes place with the magazine outside the actual testing device, by simple and low-cost means in relation to the testing device. Since contacting problems between the test piece and the testing device during the test do not block any of the testing locations of the testing device, the capacity utilization of the testing device is further increased.
The interface of the magazine devices with respect to the testing location is in this case designed in such a way that it electrically and mechanically simulates in each case a single test piece of the same or similar type of the test pieces arranged in the magazine.
Usually, a specifically configured test interface of the testing location is to be provided in this case for each type of package (TSOP, FBGA). When changing the type of test piece, conversions are necessary both at the testing locations and on the automatic placement machines.
A disadvantage of this method is the complex contacting via the side walls of the magazine device, since on the one hand it must be ensured that suitable pressure of the side wall is applied to the contact devices of the test pieces without the contact devices deforming or bending, for instance in the case of forms of package such as TSOP. On the other hand, in the case of types of package such as FBGA, at least some of the contact devices of the test piece are not readily accessible from the side.
In the same way as necessary changing of the test program, adaptation of the testing location and the automatic placement machine to the type of package again similarly contributes to the testing costs. This has until now even applied when functionally identical semiconductor devices in different types of package are tested one after the other on the same testing device.
Such converting of the placement device and testing device is an operation which is complex and time-consuming in each case and, moreover, significantly reduces the availability of the testing device.
A further disadvantage of stacking test pieces directly one on top of the other in a magazine device is the lack of convection in the magazine and the associated lack of heat dissipation from the test pieces, with the result that the temperature of the test pieces can sometimes exceed the maximum permissible limiting temperature for testing.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for testing semiconductor devices, which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provide a method with which, when testing semiconductor devices on testing devices by means of magazine devices, the number of converting operations on the testing device and on an auto
Flach Björn
Logisch Andreas
Ruf Wolfgang
Schnell Martin
Stippler Jörg
Cuneo Kamano
Greenberg Laurence A.
Hollington Jermele
Infineon - Technologies AG
Locher Ralph E.
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