Electrical computers and digital processing systems: processing – Processing control – Mode switch or change
Reexamination Certificate
2006-12-26
2006-12-26
Fleming, Fritz (Department: 2181)
Electrical computers and digital processing systems: processing
Processing control
Mode switch or change
C712S032000, C712S043000, C712S228000
Reexamination Certificate
active
07155600
ABSTRACT:
A method and logical apparatus for switching between single-threaded and multi-threaded execution states within a simultaneous multi-threaded (SMT) processor provides a mechanism for switching between single-threaded and multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. Internal control logic controls a sequence of events that ends instruction prefetching, dispatch of new instructions, interrupt processing and maintenance operations and waits for operation of the processor to complete for instructions that are in process. Then, the logic determines one or more threads to start in conformity with a thread enable state specifying the enable state of multiple threads and reallocates various resources, dividing them between threads if multiple threads are specified for further execution (multi-threaded mode) or allocating substantially all of the resources to a single thread if further execution is specified as single-threaded mode. The processor then starts execution of the remaining enabled threads.
REFERENCES:
patent: 5822602 (1998-10-01), Thusoo
patent: 6549930 (2003-04-01), Chrysos et al.
patent: 6847578 (2005-01-01), Ranganathan
patent: 2001/0054057 (2001-12-01), Long et al.
patent: 2002/0163520 (2002-11-01), Hardin et al.
patent: 2002/0194251 (2002-12-01), Richter et al.
patent: 2003/0033509 (2003-02-01), Leibholz et al.
patent: 2004/0054876 (2004-03-01), Grisenthwaite et al.
patent: 2006/0037025 (2006-02-01), Janssen et al.
Czajkowski, et al., “Resource Management for Extensible Internet Servers”, ACM SIGOPS European Workshop, p. 33-39, 1998.
Bridges, et al., “A CPU Utilization Limit for Massively Parallel MIMD Computers”, Frontiers of Massively Parallel Computing, Oct. 19-21, 1992, pp. 83-92.
Burky William Elton
Floyd Michael Stephen
Kalla Ronald Nick
Sinharoy Balaram
Fleming Fritz
Harris Andrew M.
Mitch Harris Atty at Law, LLC
Moll Jesse
Salys Casimer K.
LandOfFree
Method and logical apparatus for switching between... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and logical apparatus for switching between..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and logical apparatus for switching between... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3718172