Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-03-22
2004-06-29
Decady, Albert (Department: 2133)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000
Reexamination Certificate
active
06757186
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of generating a reference voltage. More particularly, the present invention relates to a method and logic decision device for generating a ferro-electric capacitor reference voltage.
2. Description of Related Art
A conventional method of generating a reference voltage is to use a pair of dummy cells.
FIG. 1
is a schematic circuit diagram for producing a reference voltage through a pair of dummy cells
102
and
104
. If the dummy cell
102
has an operating voltage of V
1
volts and the dummy cell
102
has an operating voltage of V
2
volts, reference voltage of the structure in
FIG. 1
is (V
1
+V
2
)/2 volts. In other words, a voltage greater than (V
1
+V
2
)/2 volts is designated as logic ‘1’ and a voltage smaller than (V
1
+V
2
)/2 is designated as logic ‘0’. However, since each capacitor has a slightly different electrical characteristic, the ferro-electric capacitor
110
inside the dummy cell
102
is charged at most to a voltage V
3
, where V
3
<V
1
. Similarly, the ferro-electric capacitor
112
is charged at most to a voltage V
4
, where V
4
<V
2
. Therefore, the actual reference voltage is (V
3
+V
4
)/2. A voltage V
5
between the voltage (V
1
+V
2
)/2 and (V
3
+V
4
)/2, is smaller than (V
1
+V
2
)/2 and hence should be regarded as being at a logic ‘0’. However, because of the capacitor property, the voltage V
5
is actually compared with the reference voltage (V
3
+V
4
)/2. Since V
5
is greater than (V
3
+V
4
)/2, this results in a logic ‘1’. When this occurs, an incorrect logical decision between ‘0’ and ‘1’ is produced. Such erroneous logical decision due to a variation in ferro-electric capacitor property often leads to an edge effect.
Another conventional method of generating a reference voltage is to use a pair of different parasitic capacitors.
FIG. 2
is a circuit diagram showing a method of deploying the voltage differential between a pair of different bit lines to produce a reference voltage.
FIG. 3
is graph showing the variation between voltage and electric charge of the ferro-electric capacitor in the circuit shown in FIG.
2
. The circuit shown in
FIG. 2
is capable of a revolving edge effect due to a variation of capacitor property. Assume the bit line
204
has an overall length greater than the bit line
208
; in other words, assume the parasitic capacitance
206
is greater than the parasitic capacitance
210
. Also assume data electric charges Q
1
waiting for logical decision sit inside the ferro-electric capacitor
202
. First, the data charges Q
1
waiting for logical decision is transferred to the parasitic capacitor
206
of the bit line
240
. Since V=Q/C, a voltage V
1
is produced. The charge/voltage inside the ferro-electric capacitor changes from point P
1
to P
2
following path A as shown in FIG.
3
.
Thereafter, reference electric charges Q
2
that represent logic ‘0’ are stored inside the ferro-electric capacitor
202
. The charge/voltage inside the ferro-electric capacitor change from P
2
to P
3
following path B as shown in FIG.
3
.
Reference electric charges Q
2
that represent logic ‘0’ are stored inside the parasitic capacitor
210
generated by the bit line
208
. The charge/voltage inside the ferro-electric capacitor changes from P
3
to P
2
following path C as shown in FIG.
3
. Since V=Q/C, voltage produced by the parasitic capacitor
210
serves as a reference voltage V
2
.
After logical decision of the waiting data, the original electric charges Q
1
waiting for a logical decision are returned to the ferro-electric capacitor
202
. The charge/voltage inside the ferro-electric capacitor change from P
2
to P
1
via points P
3
and P
4
following path D as shown in FIG.
3
.
Since V
1
is greater than V
2
, the parasitic capacitor
206
is greater than the parasitic capacitor
210
. Within a definite range, V
1
is definitely greater than V
2
. That is, data logic ‘1’ is quite obvious. Therefore, the method is very clear about the logic decision and is able to avoid edge effect problems due to a variation in capacitor property.
In brief, using identical ferro-electric capacitors for access but using a differential voltage due to the parasitic capacitor resulting from an extra length of between bit line
208
and
206
is able to avoid edge effect problem due to a variation in capacitor property. Within a definite range, logic level can be very accurately determined. Although edge effects can be avoided, other problems arise. The extra length in the bit line tends to increase volume occupation of the integrated circuit.
FIG. 4
is a schematic circuit diagram showing a system that uses an auxiliary device to produce a voltage differential and hence a reference voltage. Operating principals of the circuit are identical to the circuit shown in FIG.
2
. The only difference is that an auxiliary device instead of bit lines of different overall length is used to generate the differential voltage. As before, the auxiliary device tends also to increase volume occupation of the integrated circuit.
In short, conventional methods of generating a reference voltage lead to the following problems:
1. Edge effects due to a variation of capacitor properties; and
2. Excessive volume occupation by the integrated circuit.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of producing a reference voltage using ferro-electric capacitors so that problems in a conventional reference voltage provider such as edge effects and substantial volume occupation are reduced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of generating a reference voltage using a ferro-electric capacitor. A ferro-electric capacitor is charged so that the amount of electric charges within the ferro-electric capacitor is between the amount of electric charges for logic ‘1’ and the amount of electric charges for logic ‘0’. The electric charges are transferred to a capacitor so that a voltage is produced. The voltage produced by the capacitor is the reference voltage. The reference voltage is used to determine the logic level of data. The aforementioned ferro-electric capacitor and a ferro-electric capacitor for holding data waiting for a logical decision are identical.
This invention also provides a logic decision device that uses a reference voltage. The logic decision device includes a ferro-electric capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a first bit line, a second bit line and a micro-sensor amplifier. The ferro-electric capacitor generates a reference voltage. The first transistor is coupled to the ferro-electric capacitor serving as a switch. The second transistor is coupled to the first transistor serving as a switch. The third transistor is coupled to the first transistor and the second transistor serving as a switch. The fourth transistor is coupled to the third transistor serving as a switch. The first bit line is coupled to the second transistor serving as a parasitic capacitor. The second bit line is coupled to the third transistor and the fourth transistor serving as a parasitic capacitor. The first bit line and the second bit line has an identical length. The micro-sensor amplifier is coupled to the first bit line and the second bit line for amplifying the micro-signal and performing a logical decision.
The reference voltage is generated by charging a ferro-electric capacitor so that the ferro-electric capacitor holds an amount of electric charges intermediate between logic ‘1’ and logic ‘0’. The electric charges are then transferred to a capacitor so that the capacitor produces a voltage. The voltage produced by the capacitor is the reference voltage.
Because the amount of electric charges producing the reference voltage is intermediate between logic ‘1’ and logic ‘0’, voltage at logi
De'cady Albert
J. C. Patents
Kerveros James
Macronix International Co. Ltd.
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