Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
2001-08-28
2004-07-20
Perveen, Rehana (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S007000, C710S112000, C709S238000, C712S225000
Reexamination Certificate
active
06766386
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The field of the present invention generally pertains to the transfer of digital information in a computer system and, more particularly, to the transfer of digital information between buses in a computer system.
2. Background
The term “bus,” as used herein, generally refers to a set of hardwire lines, or conductors, used for transferring digital information among the components of a computer system. A bus may be used, for example, to transfer digital information between chips, expansion boards, and processor/memory subsystems within a computer system. A bus transaction typically involves an initiator device (the bus master), and a target device (the bus slave), each of which are interfaced to the bus. The initiator device initiates a transaction by sending command and address information over the bus to the target device, which services the transaction. For example, in a system where the initiator device is a host processor and the target device is a memory, the host processor may initiate bus transactions to read data from or write data to the target memory.
Bus transactions may be executed in a “single-transaction” mode or a “split-transaction” mode. In a single-transaction mode, the initiator device must remain committed to a given transaction until the transaction has fully completed. Consequently, an initiator device performing a write on a single-transaction bus cannot perform further transactions on the bus until the designated target device has accepted the write data. Similarly, an initiator device performing a read on a single-transaction bus cannot perform further transactions on the bus until the designated target device has returned the requested read data. In contrast, in a split-transaction mode, each bus transaction is split into two largely independent parts: a request that is issued by the initiator device and a reply that is issued by the target device. As a result, an initiator device operating on a split-transaction bus is free to perform other transactions on the bus after issuing a request, even though a reply has not yet been received from the designated target device.
The PCI bus, as defined by the PCI Local Bus Specification Rev. 2.2 (published by the PCI Special Interest Group), is an example of a bus architecture that utilizes a single-transaction method of operation. In accordance with PCI bus protocols, when a target device requires an extended period of time to respond to a transaction, it may suspend the transaction so that the PCI bus can be used by other devices to perform other transfer operations in the interim. The suspension of the transaction by the target is termed a “disconnect.” Because the PCI bus is a single-transaction bus, the initiator device will continue to “retry” the transaction in response to the disconnect until such time as the transaction may complete.
Where the initiator device is the bridge between a CPU or other host device and the PCI bus, the inability of the initiator device to make further PCI bus accesses until the transaction has completed can result in a degradation of system bandwidth. To address this issue, conventional PCI bus bridges offer the ability to post, or queue, write operations from the initiator device, thus permitting a host CPU to issue writes and then continue on to issue other bus transactions without delay. Unfortunately, the read path is not amenable to such a solution. If the desired data from the target device is not read-cacheable, as in the case of data from real-time status registers or read-modified memories such as FIFOs, the host must wait for the read data to be produced by the target device before it can perform further transactions on the PCI bus. As a result, a target device that is slow to respond to PCI reads will essentially force the CPU to wait while the host-PCI bus bridge retries the read until it completes.
When bridging a single transaction bus, such as the PCI bus, to a split-transaction bus, the latency for producing read data can be substantial since a request for read data must be sent and a response received on the split-transaction bus before the read data can be presented to the PCI side of the bridge. This latency equates directly to a loss of CPU bandwidth when a host CPU on the PCI bus is attempting to read registers or other memories on the split-transaction bus that store non-cacheable data.
This concept may be illustrated in reference to
FIG. 1
, which depicts a conventional single-transaction to split-transaction bus bridge application
100
. As shown in
FIG. 1
, a host CPU
102
resides on a single-transaction bus
104
and a set of registers
106
resides on a split-transaction bus
108
. The single-transaction bus
104
is interfaced to the split-transaction bus
108
via the conventional bus bridge
110
. The conventional bus bridge
110
includes a bridge control state machine
114
that provides the necessary handshaking functionality between the single-transaction bus
104
and the split-transaction bus
108
, and a read FIFO
112
for the temporary buffering of requested read data retrieved from the split-transaction bus
108
for immediate transfer over the single-transaction bus
104
.
FIG. 2
depicts the potential latencies involved when the host CPU
102
of
FIG. 1
performs a direct read access to the bus bridge
110
to obtain data from the registers
106
. In particular,
FIG. 2
shows potential bus activity on the single transaction bus
104
and the split-transaction bus
108
during such an access. As shown in
FIG. 2
, after the host CPU
102
initiates a read to the bus bridge
110
at block
202
a
, the bus bridge
110
responds by issuing a read request on the split-transaction bus
108
, shown in block
206
. Because the bus bridge
110
must wait to receive a read response from the registers
106
, the bus bridge
110
eventually issues a disconnect to the host CPU
102
. In response to the disconnect, the host CPU
102
will continue issuing reads to the bus bridge
110
in accordance with a single-transaction mode of operation. If the time required for the bus bridge
110
to receive a read response from the registers
106
is long, the host CPU
102
may receive numerous disconnects. These attempted reads and disconnects are denoted as blocks
202
a
through
202
n
in FIG.
2
. Eventually, the bus bridge
110
receives a read response from the registers
106
, as shown in block
208
, and the requested data is transferred from the registers
106
to the read FIFO
112
in the bus bridge
110
. Because the data is now available in the bus bridge
110
, the data will be transferred from the bus bridge
100
to the host CPU
102
during the next attempted read by the host CPU
102
and the read will complete, as shown in block
204
.
The total latency for this example read data transfer is equal to the time periods d
1
+d
2
+d
3
denoted in FIG.
2
. The time period d
1
corresponds to the latency involved in issuing the read request on the split-transaction bus
108
. The time period d
2
is the latency involved in receiving a response and read data from the registers
106
over the split-transaction bus
108
. Finally, the time period d
3
is the latency between the time that the bus bridge
110
receives the response and read data from the registers
106
and the time that the host CPU
102
retries the read access and the read completes.
As illustrated by
FIG. 2
, the time period d
2
represents the largest portion of the total latency and is roughly equal to the amount of CPU processing time wasted waiting for the read data to emerge. This waste of bandwidth becomes significant in applications where a memory on the split-transaction bus is read repeatedly and often by a host CPU. An example of this may be found in a cable modem termination system (CMTS) line card application in which a host processor is coupled via a PCI bus to a BCM3212 CMTS MAC integrated circuit (IC) manufactured by Broadcom Corporation of Irvine, Calif. In such an application, it is contemp
Danzig Joel
Dobson William Gordon Keith
Broadcom Corporation
Mai Rijue
Perveen Rehana
Sterne Kessler Goldstein & Fox P.L.L.C.
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