Static information storage and retrieval – Read/write circuit – Simultaneous operations
Reexamination Certificate
2003-10-24
2004-11-30
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Simultaneous operations
C365S230030, C365S189060, C365S233100, C365S230060
Reexamination Certificate
active
06826088
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit, and more particularly to an integrated circuit capable of reading and writing data simultaneously with a separate input and output port and a method of simultaneously reading and writing data.
2. Description of the Related Art
A general synchronous RAM can transmit either read data or write data in synchronization with each pulse of a clock signal.
A double data rate RAM increases the data transmission rate to twice the existing transmission rate by transmitting data at every rising edge and falling edge of a clock signal. In a general memory device, however, data is input and output through one pin. When data is input and output through a common input and output (I/O) port, data input or output cannot be independently controlled. Thus, the frequencies of data input or output are limited.
Because the bandwidth of a memory device has become increasingly important, a memory device having a separate I/O port has been produced. That is, input pins and output pins are separated so that data input and output can be independently controlled. Since a memory device having separate I/O ports can receive a read command, a read address, a write command, a write address, and write data in one period of a clock signal, the operational frequency can increase.
In order to read or write data within one period of a clock signal, however, a memory device having separate I/O has to access a memory cell two times.
That is, since a word line for reading and writing data is activated two times within a period of the clock signal, a clock signal frequency is limited by the time necessary for activating the word line.
FIG. 1
is a timing diagram for explaining an operation of a memory device having separate I/O ports.
Since a relation between an address and a word line and latency of input data and output data may be changed according to a circuit configuration of a memory device, they will not be considered in FIG.
1
.
Referring to
FIG. 1
, a write address and a read address are both input in the same period of a clock signal CLK. Addresses A
0
, A
2
, A
4
, and A
6
, which are input at a rising edge of the clock signal CLK, are the read addresses RADD, and addresses A
1
, A
3
, A
5
, and A
7
, which are input at a falling edge of the clock signal CLK, are the write addresses WADD.
RES denotes a read selection signal used to select the read address RADD, and WES denotes a write selection signal used to select the write address WADD.
A word line AWL
0
is activated by a read address RADD A
0
, and data Q
0
is output in response to the word line AWL
0
. In addition, after a word line AWL
1
is activated in response to a write address WADD A
1
, input data D
1
is input.
Therefore, the length of a period of the clock signal CLK is limited due to activations of the word line AWL
0
for data read and the word line AWL
1
for data write. That is, since it is necessary to sequentially access memory cells having different addresses during a period of the clock signal CLK, it is difficult to reduce the period of the clock signal CLK.
SUMMARY OF THE INVENTION
The present invention provides an integrated circuit that is capable of increasing an operational frequency of a clock signal by sequentially reading data from and writing data to a memory cell within a period of the clock signal.
The present invention also provides a method of increasing an operational frequency of a clock signal by sequentially reading data from and writing data to a memory cell within a period of the clock signal.
According to one aspect of the present invention, there is provided an integrated circuit that has separate input and output ports and to which a write address and a read address are input during a period of a clock signal, the integrated circuit comprising memory blocks that respectively include a plurality of sub memory blocks, cache memory blocks that respectively correspond to the memory blocks, and a tag memory control unit that reads data from or writes data to the memory blocks and the cache memory blocks in response to the write address or the read address, wherein the tag memory control unit reads data from or writes data to a memory block and a cache memory block at the same time if an upper address of the read address and an upper address of the write address are identical to each other.
Two different sub memory blocks respectively corresponding to the write address and the read address are decoded.
The integrated circuit further comprises a write address decoding path and a read address decoding path that are separated from each other, and the sub memory blocks are connected to the write address decoding path and the read address decoding path.
Among the sub memory blocks in the memory block, memory cells having the same upper address correspond to one memory cell of the cache memory block. The size of the cache memory block is equal to or is larger than the size of the sub memory block.
The tag memory control unit stores validity determination information used to determine whether a cache memory address, which indicates an address of the sub memory block corresponding to the cache memory block and the data stored therein, and the cache memory block are valid or not.
When data is read and written simultaneously, the tag memory unit directs simultaneous data operations based on the upper read and write addresses. In one case, the upper read and write addresses are identical, but both differ from the cache memory address. In this case, the tag memory control unit reads data from the memory block corresponding to the read address and writes data to the cache memory block.
In a second case, the upper read and write addresses are identical, but either the write address or the read address is identical to the cache memory address. In this case, the operation corresponding to the address that is identical to the cache memory address is performed on the cache memory block, and the other operation is performed on the memory block. In a third case, if the read address, write address, and cache memory address are all identical, data is read from the cache memory block and written to the memory block at the same time.
In a fourth case, the upper read address and upper write address are not identical, but either the write address or the read address is identical to the cache memory address. In this case, an operation corresponding to the address that is identical to the cache memory is performed on the cache memory block, and the operation corresponding to the other address that is not identical to the cache memory address is performed on the memory block.
The data is input or output at a single data rate (SDR) or a double data rate (DDR).
According to another aspect of the present invention, there is provided an integrated circuit that has separate input and output ports, the integrated circuit comprising memory blocks that respectively include a plurality of sub memory blocks, a plurality of cache memory blocks that respectively correspond to the memory blocks and to which data are read or written in response to a cache control signal, a plurality of decoding units that respectively correspond to the memory blocks and generate decoding signals used to control the sub memory blocks in response to a write address, a read address, or a decoding control signal, a tag memory control unit which receives a write selection signal or a read selection signal, receives the write address or the read address, and generates the cache control signal or the decoding control signal to read or write data based on whether the write address and the read address are identical to each other during a period of a clock signal.
The decoding units include a plurality of decoding circuits that correspond to the sub memory blocks. The decoding circuits are connected to a write address decoding path and a read address decoding path that are separated from each other, and the sub memory blocks are respectively connected to the write address d
Sohn Kyo-Min
Suh Young-Ho
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