Method and implementation of stress test for MRAM

Details Method and implementation of stress test for MRAM Method and implementation of stress test for MRAM

2007-09-27

2009-10-27

Lam, David (Department: 2827)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S148000, C365S201000, C365S210100

Reexamination Certificate

active

07609543

ABSTRACT:
Voltage and current stress for magnetic random access memory (MRAM) cells can weed out potential early failure cells. Method and circuit implementation of such a stress test for a MRAM comprise coupling a stress test circuit to the read bus of the MRAM and stressing the Magnetic Tunnel Junctions (MTJS) by tying them to ground by activating isolation transistors associated with them. Read word lines control which MTJs are stressed Both the method and implementation can be used for any memory cells based on resistance differences, such as Phase RAM or Spin Valve MRAM.

REFERENCES:
patent: 6347056 (2002-02-01), Ledford et al.
patent: 6760865 (2004-07-01), Ledford et al.
patent: 6831872 (2004-12-01), Matsuoka
patent: 6862213 (2005-03-01), Hamaguchi
patent: 6894937 (2005-05-01), Garni et al.
patent: 6990024 (2006-01-01), Hidaka
patent: 2007/0115717 (2007-05-01), Yang et al.

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