Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1995-02-03
1997-07-22
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
370503, H04L 1252
Patent
active
056510349
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a method and to an equipment for monitoring the fill rate of an elastic buffer memory.
The current digital transmission network is plesiochronous, that is, e.g. each 2-Mbit/s basic multiplex system has a dedicated clock independent of any other system. It is therefore impossible to locate a single 2-Mbit/s signal in the bit stream of a higher-order system, but the higher-level signal has to be demultiplexed through each intermediate level down to the 2 Mbit/s level to extract the 2-Mbit/s signal. For this reason, especially the construction of branch connections requiring several multiplexers and demultiplexers has been expensive. Another disadvantage of the plesiochronous transmission network is that equipments from two different manufacturers are not usually compatible.
The above drawbacks, among other things, have led to the introduction of the new synchronous digital hierarchy SDH specified e.g. in the CCITT specifications G.707, G.708 and G.709. The synchronous digital hierarchy is based on STM-N transfer frames (Synchronous Transport Modules) located on several levels of hierarchy N (N=1,4,16 . . . ). Existing PCM systems, such as 2-, 8- and 32-Mbit/s systems are multiplexed into a synchronous 155.520-Mbit/s frame of the lowest level of the SDH (N=1). Consistently with the above, this frame is called the STM-1 frame. On the higher levels of hierarchy the bit rates are multiples of the bit rate of the lowest level.
FIG. 1 illustrates the structure of the STM-N frame, and FIG. 2 illustrates a single STM-1 frame. The STM-N frame comprises a matrix with 9 rows and N.times.270 columns so that there is one byte at the junction point between each row and the column. Rows 1-3 and rows 5-9 of the N.times.9 first columns comprise a section overhead SOH, and the row 4 comprises an AU pointer. The rest of the frame structure is formed of a section having the length of N.times.261 columns and containing the payload section of the STM-N frame.
FIG. 2 illustrates a single STM-1 frame which is 270 bytes in length, as described above. The payload section comprises one or more administration units AU. In the specific case shown in the figure, the payload section consists of the administration unit AU-4, into which a virtual container VC-4 is inserted. (Alternatively, the STM-1 transfer frame may contain several lower-level administration units (AU-3) each containing a corresponding lower-level virtual container (VC-3)). The VC-4 in turn consists of a path overhead POH located at the beginning of each row and having the length of one byte (9 bytes altogether), and of the payload section in which there are lower-level frames also comprising bytes allowing interface justification to be performed in connection with mapping when the rate of the information signal to be mapped deviates from its nominal value to some extent. Mapping of the information signal into the STM-1 frame is described e.g. in the patent applications AU-B-34689/89 and FI-914746.
Each byte in the AU-4 unit has its own location number. The above-mentioned AU pointer contains the location of the first byte of the VC-4 container in the AU-4 unit. The pointers allow positive or negative pointer justifications to be performed at different points in the SDH network. If a virtual container having a certain clock frequency is applied to a network node operating at a clock frequency lower than the above-mentioned clock frequency of the virtual container, the data buffer will be filled up. This requires negative justification: one byte is transferred from the received virtual container into the overhead section while the pointer value is decreased by one. If the rate of the received virtual container is lower than the clock rate of the node, the data buffer tends to be emptied, which calls for positive justification: a stuff byte is added to the received virtual container and the pointer value is incremented by one.
FIG. 3 shows how the STM-N frame can be formed of existing asynchronous bit streams. These bit
REFERENCES:
patent: 5067126 (1991-11-01), Moore
patent: 5091907 (1992-02-01), Wettengel
Oksanen Toni
Viitanen Esa
Chin Stephen
Nokia Telecommunications Oy
Phan Hai H.
LandOfFree
Method and equipment for monitoring the fill rate of an elastic does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and equipment for monitoring the fill rate of an elastic , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and equipment for monitoring the fill rate of an elastic will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1565110