Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-03-28
1999-11-30
Le, Dieu-Minh T.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 53, 714805, G06F 1100
Patent
active
059960930
ABSTRACT:
A method and a device for determining that digital information written into a memory is correctly readable before such read information, in the form of a number of coordinated bit positions, is used to control one or several functions, where the functions can be activated by a computer unit. A selected address position or positions within the memory corresponding to the stored digital information points out a first set of bits, required to control and/or initiate the functions, and a second set of bits serving as a control sum. The second set of bits is calculated taking into consideration the current set of bits corresponding to the first set of bits and a third set of bits, corresponding to the address position currently selected for readout. When the following readout of the digital information out of the memory is performed, a new control sum is calculated in the same way, taking into consideration the currently read bit positions corresponding to the first set of bits and a fourth set of bits corresponding to the address position currently selected for readout, to form a fifth set of bits. The read digital information is accepted as correct when a comparison is performed and agreement is found between the second set of bits and the fifth set of bits.
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Le Dieu-Minh T.
Telefonaktiebolaget LM Ericsson
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