Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reexamination Certificate
2007-04-06
2009-02-24
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C438S017000, C438S018000, C438S401000, C438S462000, C257S797000, C257SE23179
Reexamination Certificate
active
07494830
ABSTRACT:
A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through the wafer from the backside to perform an alignment process with the first test structure; and determining an overlay accuracy of the alignment process with the second test structure. The first test structure includes an optical vernier and the second test structure includes an electrical testing structure.
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Chou Hsueh-Liang
Chu Jeffery
Kao Chia-Hung
Lee Ya-Wen
Liu Sheng-Chieh
Fourson George
Haynes and Boone LLP
Taiwan Semiconductor Manufacturing Company
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