Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry
Reexamination Certificate
1997-12-16
2001-01-23
Yoo, Do Hyun (Department: 2759)
Electrical computers and digital processing systems: memory
Address formation
Incrementing, decrementing, or shifting circuitry
C711S218000, C710S052000
Reexamination Certificate
active
06178490
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the memories of the central processing units of microcomputers and more particularly to a method and device for the incremental reading of a memory so as to improve its performance characteristics by increasing the data output speed, should the reading be done at consecutive addresses of the memory in the mode known as the “burst read” mode.
2. Discussion of Related Art
Pieces of data contained in a memory are read by means of addresses or addressing codes that are provided successively to addressing circuits of the memory by the central processing unit of the microprocessor or microcontroller, each addressing code corresponding to a piece of data that is then processed by the central processing unit according to the instruction being executed. In this mode of reading, the pieces of data contained in the memory are read only as and when the addressing codes arrive, the addressing code of the next piece of data to be processed being provided only after the transfer of the previous piece of data into the central processing unit.
This read mode results in idle time during reading of the memory and therefore results in a time delay. This time delay is detrimental to the speed of computation of the central processing unit.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to reduce this reading time and thus increase the data output speed.
To achieve this aim, one embodiment of the invention reads a piece of data at an address immediately following the reading of the piece of data contained in the following address, the latter address being obtained by incrementing the previous address by one unit.
Thus, in performing an instruction that uses the pieces of data contained at consecutive addresses of the memory, it is not necessary to wait for the arrival of the addressing code coming from the central processing unit to read the memory at these consecutive addresses.
Should the address given by the central processing unit not correspond to the next address of the memory, the data read at this last address is not transferred to the central processing unit and is therefore not taken into account.
To implement a method according to the invention, the addressing and read circuits of the memory must be modified or added to.
Thus, the read circuits may include, apart from the read register, an additional register called a data register to record the piece of data read and thus free the read register for the reading at the following address and electronic transfer circuits between the read register and the data register to obtain the passage of the data from the read register to the data register.
Furthermore, the addressing register of the memory may be of the incremental type, the incrementation being activated by a signal provided by a sequencing circuit. This sequencing circuit provides another signal furthermore controlling the electronic transfer circuits between the read register and the data register.
The invention therefore relates to a device for the incremental reading of a memory of a central processing unit of a microcomputer with which there are associated circuits for the addressing of the cells of said memory comprising an address register and circuits for the reading of the signals read in the cells of the memory selected by said addressing circuits comprising a first register called a read register in which the signals read are recorded in binary form, wherein the device comprises an incrementation circuit for increasing the contents of the address register by at least one unit so that it addresses the memory cells corresponding to the address that follows the one that it contains, and a storage circuit for recording the contents of the read register so that it can record the signals read in the memory cells corresponding to the next address.
In another embodiment, the incrementation circuit includes a sequencing circuit that is controlled by the signals given by the central processing unit and that provides a signal for the incrementation of the address register.
The storage circuit to record the contents of the read register includes a second register called a data register and electronic transfer circuits that are controlled by a signal provided by the incrementation circuit of the address register.
The invention also relates to a method for the incremental reading of a memory of a central processing unit of a microcomputer with which there are associated circuits for the addressing of the cells of said memory, comprising an address register, and read circuits for the reading of the signals read in the cells of said memory selected by said addressing circuits, comprising a first register called a read register in which the signals read are recorded in binary form, wherein said method comprises the following steps:
a) recording, by the central processing unit, an addressing code in the address register;
b) reading the cells of the memory selected by the addressing code;
c) recording signals read during the step b) in the read register and then in a second register called a data register;
d) transferring the contents of the data register to the central processing unit;
e) incrementing, by at least one unit, the contents of the address register to obtain a new addressing code;
f) reading the memory cells selected by the new addressing code obtained by step e);
g) recording the signals read during the step f) in the read register and then in the data register;
h) transferring the contents of the data register to the central processing unit if the next addressing code corresponds to the address resulting from the step e), and then returning to step e); and
i) returning to step a) if the next addressing code does not correspond to the address resulting from step e).
In one embodiment of the method, the incrementing step e) is performed between steps c) and d).
REFERENCES:
patent: 4617660 (1986-10-01), Sakamoto
patent: 5465343 (1995-11-01), Henson et al.
patent: 5745791 (1998-04-01), Peek et al.
patent: 5805518 (1998-09-01), Hashimoto et al.
patent: 5892730 (1999-04-01), Sato et al.
De Ferron G{acute over (e)}rard Silvestre
Gaultier Jean-Marie
Galanthay Theodore E.
Moazzami Nasser
Morris James H.
SGS-Thomson Microelectronics S.A.
Wolf Greenfield & Sacks P.C.
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