Method and device for testing for the occurrence of bit errors

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data pulse evaluation/bit decision

Reexamination Certificate

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C714S724000

Reexamination Certificate

active

10686693

ABSTRACT:
In a method and a device for testing a plurality of measured devices in parallel by using a single signal generator and a single bit error measuring device, a serial testing signal for is converted and demultiplexed into parallel signals corresponding to channels respectively assigned to a plurality of measured devices and a redundant channel, one of the plurality of parallel signals being a passing signal passing through the redundant channel is converted into a channel determination signal for specifying an alignment of the measured devices, output signals of the measured devices and the channel determination signal are multiplexed corresponding to a demultiplexing mode used for demultiplexing the serial signal, and bit errors are measured in the multiplexed signals and measured devices at which the bit errors are generated are detected in consideration of the channel determination signal.

REFERENCES:
patent: 5566193 (1996-10-01), Cloonan
patent: 6094737 (2000-07-01), Fukasawa
patent: 56-155551 (1981-11-01), None
patent: 60-033757 (1985-02-01), None
patent: 64-064430 (1989-03-01), None
patent: 2002223204 (2002-08-01), None

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