Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2007-01-23
2007-01-23
Nguyen, Viet Q. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Testing
C365S230090, C365S221000, C365S219000, C365S220000, C714S742000, C714S733000, C714S725000, C714S763000, C714S819000
Reexamination Certificate
active
10436895
ABSTRACT:
A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or row of the configuration memory array, and an input data storage device for storing configuration data required to be stored in the selected column or row, or test data for testing the selected column or row. The PLD may also include an output data storage device for storing the output from the selected column or row, and test logic that provides control signals for verifying the correct operation of the data lines of the configuration memory array without disturbing the data stored in the memory array.
REFERENCES:
patent: 5430687 (1995-07-01), Hung et al.
patent: 5583450 (1996-12-01), Trimberger et al.
patent: 5646546 (1997-07-01), Bertolet et al.
patent: 5732407 (1998-03-01), Mason et al.
patent: 5778256 (1998-07-01), Darbee
patent: 5841867 (1998-11-01), Jacobson et al.
patent: 5970005 (1999-10-01), Yin et al.
patent: 6009256 (1999-12-01), Tseng et al.
patent: 6057704 (2000-05-01), New et al.
patent: 6191614 (2001-02-01), Schultz et al.
patent: 6195774 (2001-02-01), Jacobson
patent: 6237124 (2001-05-01), Plants
patent: 6262596 (2001-07-01), Schultz et al.
patent: 6278290 (2001-08-01), Young
patent: 6429682 (2002-08-01), Schultz et al.
patent: 6539508 (2003-03-01), Patrie et al.
patent: 6664807 (2003-12-01), Crotty et al.
patent: 6774667 (2004-08-01), Chan
patent: 6774669 (2004-08-01), Liu et al.
patent: 6774672 (2004-08-01), Lien et al.
patent: 6817006 (2004-11-01), Wells et al.
patent: 6864712 (2005-03-01), Agarwal et al.
patent: 6891395 (2005-05-01), Wells et al.
patent: 6985096 (2006-01-01), Sasaki et al.
patent: 2005/0144215 (2005-06-01), Simkins et al.
patent: 410097511 (1998-04-01), None
patent: 02000030499 (2000-01-01), None
Pathak Shalini
Swami Parvesh
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Nguyen Viet Q.
STMicroelectronics Pvt Ltd.
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