Electrical computers and digital processing systems: memory – Storage accessing and control
Patent
1993-01-07
1998-10-27
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
711 5, 711153, 711154, G06F 1200
Patent
active
058290095
ABSTRACT:
A memory device implementing a Kanerva memory system is provided having an address space (12) and key addresses (14) therein. The key addresses (14) partition the address space (12) such that a hypersphere (17) defined by a radius of capture (16) for each key address (14) does not overlap a hypersphere (17) of any other key address (14). By such partitioning, at most one key address (14) can be activated during a read or write operation. Each key address (14) has an address decoder (24) determining if an input address falls within the hypersphere (17) of the key address (14). If so, the key address (14) is activated and a memory element (26) within each key address (14) stores the address data within multiple bit binary counters (28) by incrementing upon storing a binary 1 and decrementing upon storing a binary 0 during a write operation. In read mode, the contents of multiple bit binary counters (28) are transferred out of the memory device (10).
REFERENCES:
"Notes on Implementation of Sparsely Distributed Memory" by Keeler et al, Aug. 7, 1986, Research Institute for Advanced Computer Science, pp. 1-22.
"Kanerva's Sparse Distributed Memory: An Associative Memroy Algorithm Well-Suited to the Connection Machine" by Rogers, International Journal Of High Speed Computing, vol. 1, No. 2 (1989) pp. 349-365.
"Configurable Sparse Distributed Memory Hardware Implementation" by Lindell et al, 1991 IEEE International Symposium on CRTs & Systems, pp. 3078-3081 vol. 5.
"VLSI Architectures of Sparse Distributed Memory" by Saarinen et al 1991 IEEE International Symposium on CRTs & Systems, pp. 3074-3077 vol. 5.
Donaldson Richard L.
Holland Robby T.
Swann Tod R.
Texas Instruments Incorporated
Thai Toan V.
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