Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration – Loading initialization program
Reexamination Certificate
1999-12-14
2001-08-07
Riley, Shawn (Department: 2838)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
Loading initialization program
Reexamination Certificate
active
06272630
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and device for a power on/off control, and more particularly to a method and device for reserving wake-up functions of a personal computer after a power loss.
BACKGROUND OF THE INVENTION
Intel® has provided a specification, ATX, for the personal computer industry. The ATX motherboard provides several functions such as soft-off, timer-on, and multi-wake-up functions such as waked up by the modem, LAN, mouse, and keyboard . . . etc. The ATX motherboard is also compatible with the PC98 specification and the advance configuration and power interface (ACPI). Conventionally, a computer system may have two global system states: a mechanical off state and a working state. However, a computer with an ATX motherboard may be in a mechanical off state, a soft-off state, a sleeping state or a working state. This may meet problems in a power-loss situation. At the beginning, an Intel chipset can only provides a working state for the ATX computer when the power is supplied again. However, in many situations, a working state is not expected. To solve the problem, Intel provides a circuit for the user to determine whether the system is in a working state or a soft-off state when the power is provided again.
However, there still exists some problems. When the power is lost, some parameters needed for the system operation may be lost. These parameters are provided by BIOS and may be adjusted by the user. Unless the system is reset, these parameters cannot be recovered. If a soft-off state is chosen by an Intel chipset user, these parameters cannot be recovered unless the user presses the bottom to reset the system.
An ATX power supply can be in a waiting state to wait for a wake-up event. A waiting voltage 5VSB is provided by the ATX power supply to the system to enable the wake-up ability. A signal SUSC is outputted by the chipset. When the signal SUSC is inactive, the chipset identifies that the system is in a working state. Oppositely, if the signal SUSC is active, it represents that the chipset identifies that the system is in a waiting state which is capable of executing an wake-up event. However, the conventional chipset cannot properly generate a correct SUSC signal after a power loss. For example, an Intel PIIX4 south-bridge chipset can only generate an inactive SUSC signal when the waiting voltage 5VSB is lost and provided again, no matter whether the system is in a working state or a waiting state. Consequently, the data needed for the wake-up event is lost and cannot be reset since the chipset identifies that the system is in a working state even if it is actually in a waiting state. Unless the user presses the panel button to restart the computer, the wake-up functions will be invalid.
Such a process is relatively inconvenient for the user. For example, a timer-on function is set that the computer is turned on at 6:00 a.m. and a power-loss happens at midnight. Although the power may be supplied again before 6:00 a.m., the timer-on function still cannot be executed since the parameter about when to turn on the computer is lost. Other functions about the wake-up event cannot be executed because of the same reason.
It is then attempted by the present invention to solve the above-mentioned problems.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a device for ensuring the execution of a wake-up event of a system after a power loss.
Another object of the present invention is to provide a device for control the on/off state of a computer compatible with the ATX specification.
Still another object of the present invention is to provide a device that can automatically reset the chipset after a power loss.
In addition, the present invention provides a method for maintaining a wake-up function of a computer having a chipset in a waiting state after a power loss. To reset the chipset, the computer is firstly turned on when power is supplied again. Accordingly, the parameters associated with the wake-up functions are restored. Then, an override power-off signal is provided to switch the computer to a waiting state capable of executing these wake-up functions.
The computer is preferably compatible to an ATX specification and an advanced configuration and power interface (ACPI) specification. According to the ACPI specification, the override power-off signal is an output signal lasting for 4 seconds.
The output signal is outputted to the chipset to switch the SUSC signal of the chipset to an inactive state. To enable the original button-control functions, the output signal is preferably executed a logic AND operation with a panel switch output signal of the computer before outputted to the chipset.
The chipset identifies that the computer is in a waiting state according to the inactive output signal. The computer is then switched to the waiting state.
The device of the present invention includes a power detecting device and a power-control device. The power detecting device is a circuit for detecting the power loss and generating a first signal when the power is supplied again. The power-control device turns on the computer according to the first signal to reset the chipset, and then switches the computer to a waiting state capable of executing the wake-up functions.
The computer may further include an ATX power supply electrically connected to the chipset, the power detecting device, and the power-control device. Preferably, the computer is also compatible to an ACPI specification.
The power-control device preferably switches the computer to the waiting state according to a second signal outputted by the chipset. The second signal is preferably an SUSC signal. The power-control device switches the computer to the waiting state when the SUSC signal is in an inactive state.
A third signal is preferably outputted from the power-control device to the chipset in response to the first signal. The third signal is kept in an inactive state for a specific period of time to switch the second signal into the inactive state. The specific period of time is preferably 4 seconds.
The device of the present invention may further include a panel switch control device electrically connected between the power-control device and the chipset. The third signal, instead of being directly outputted to the button-in terminal of the chipset, may be sent to the panel switch control device for being executed therein a logic AND operation with a panel switch output signal to obtain a fourth signal to be outputted to the chipset.
When the power-detecting device detects a power loss, a battery voltage is preferably supplied to the computer for reserving an operation configuration of the computer before the power is lost.
The power-control device may further include an enabling terminal for enabling the power-control device.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which:
REFERENCES:
patent: 5327531 (1994-07-01), Bealkowski et al.
patent: 6081890 (2000-06-01), Datta
Chen Tseng-Wen
Wang Cheng-Chih
Riley Shawn
Winbond Electronics Corporation
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