Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1998-06-09
2000-05-23
Nelms, David
Static information storage and retrieval
Read/write circuit
Bad bit
36523003, G11C 700
Patent
active
060672595
ABSTRACT:
A fault repair method including the steps of providing second memory cells as spare lines for repairing faulty elements of first memory cells for storing data therein, setting virtual third memory cells with respect to a repair target including said first memory cells and the second memory cells, and repairing the faulty elements of the first memory cells and the second memory cells by using the virtual third cells.
REFERENCES:
patent: 4908798 (1990-03-01), Urai
patent: 5859804 (1999-01-01), Hedberg et al.
N. Hasan, et al., "Minimum Fault Covering in Reconfigurable Arrays", Integration, the VLSI journal 11(1991), pp. 215-234.
Chor-Ping Low, et al., "Minimum Fault Coverage in Memory Arrays: A Fast Algorithm and Probabilistic Analysis", IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 15, No. 6, Jun. 1996, pp. 681-690.
S.Y.Kuo, et al., "Efficient Spare Allocation for Reconfigurable Arrays", IEEE Design & Test, vol. 4, No. 1, Feb. 1987, pp. 24-31.
W.K. Fuchs, et al., "Defect-and Fault-Tolerant Memories-Diagnosis and Repair of Large Memories: A Critical Review and Recent Results", Proc. Int'l Workshop on Defect and Fault Tolerance in VLSI Systems, (1989), pp. 213-225.
Handa Keiichi
Haruki Kazuhito
Ho Hoai V.
Kabushiki Kaisha Toshiba
Nelms David
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