Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-11-05
2002-02-26
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C709S208000
Reexamination Certificate
active
06351823
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and a device for monitoring an operation of a computer system that has at least two processors.
BACKGROUND INFORMATION
A conventional device is described in German Patent No. 37 00 986. In particular, this German Patent describes a computer system having two processors, which contribute equally to the processing work of the entire system. To be able to recognize in a timely manner the errors that arise, the two processors reciprocally monitor each other. This monitoring proceeds in the course of a cyclical data exchange between the two processors in the form of a handshake operation. In this context, it is possible that each processor may restart the other, e.g., after the cessation of an interference effect regarding the I/O bus of one of the two processors or in response to a long-lasting total failure of one of the two processors. In addition to the monitoring by means of a cyclical data exchange, provision is made for a first and a second pump circuit, each of which is assigned to a processor. With a positive logic as the basis, the two pump circuits each supply a logic 1, as long as they are controlled by a timing signal of the respective assigned processor. The monitoring of the output signals from each pump circuit by the other respective processor offers a second possibility for reciprocal monitoring, in the form of a watchdog circuit.
The conventional device described above makes it possible to reciprocally (and reliably) monitor two processors, which can execute tasks that either are of equal status or are subordinated, one to the other. However, if one of the two processors is not needed during a time period either known in advance or expectable, in order to reduce the power loss, it would be useful during this time period to switch from this operating mode to one which uses less energy, such so-called power-save modes in processors are already known and can, in many cases, be activated and deactivated via an external control input. During such a power-save mode, a processor generally does not carry out any operations, which results in substantially reducing the use of current and thus also of power compared to a normal operating mode. However, this means that during a power-save mode of this type no operations for monitoring another processor are possible. In the case of the arrangement described in German Patent No. 37 00 986, it is therefore not possible to shift one of the processors into a power-save mode, without giving up the continuous monitoring function of the other processor.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a device and a method in which an error-free functioning of the computer system is assured even when one processor participating in the reciprocal monitoring is put into a power-save mode.
The idea underlying the present invention is that monitoring an operation of a processor can be dispensed with for as long as no external effects proceed from it. In technical terms, this means that the monitoring can be dispensed with for as long as the monitored processor does not transmit any output signals to other units. Such other units can be, for example, other computers in a network or final control elements in a closed-loop control system. A device and a method are indicated in which the output signal of the monitored processor is blocked for as long as the monitoring processor is in a power-save mode.
One of the advantages of the present invention is that monitoring of the operation of a processor is dependably provided by a further processor even when the monitoring processor is shifted into a power-save mode. A device according to the present invention thus makes it possible to reduce power loss while maintaining undiminished monitoring of the operation. This is particularly necessary in the use of a multi-processor system in a motor vehicle. At the same time, the method and device according to the present invention can be realized cost-effectively, in a very simple manner, and with minimal outlays.
REFERENCES:
patent: 4598356 (1986-07-01), Dean et al.
patent: 5016249 (1991-05-01), Hurst et al.
patent: 5367665 (1994-11-01), Koch et al.
patent: 5367697 (1994-11-01), Barlow et al.
patent: 5436837 (1995-07-01), Gerstung et al.
patent: 5526267 (1996-06-01), Sogawa
patent: 5987365 (1999-11-01), Okamoto
patent: 6067586 (2000-05-01), Ziegler et al.
Hellmann Manfred
Lauxmann Ralph
Mayer Hermann
Winner Hermann
Iqbal Nadeem
Kenyon & Kenyon
Robert & Bosch GmbH
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