Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2006-11-28
2006-11-28
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C365S233100
Reexamination Certificate
active
07143258
ABSTRACT:
A DDR SDRAM operates at a double data rate by accessing the bursts of data having a burst length in accordance with the rising and falling edges of each pulse of a DQS signal. A ringing may occur in the DQS signal causing write failures. To mask the ringing, a DQS buffer generates a first access signal at the rising edge of each DQS pulse generated in presence of the data burst. The DQS buffer also generates a second access signal at the falling edge of each DQS pulse. Each of the first and second access signals includes a finite number of pulses based on the total number of rising and falling edges of the DQS signal. Two consecutive data bursts are accessed together for a write operation for each pair of the consecutive first and second access signals. After accessing all data bursts, a mask time is calculated to disable the DQS buffer, by which the ringing is masked.
REFERENCES:
patent: 6134179 (2000-10-01), Ooishi
patent: 6560669 (2003-05-01), Ryan
patent: 2004/0052151 (2004-03-01), Jacobs et al.
patent: 2004/0268028 (2004-12-01), Lee
patent: 2005002521 (2005-06-01), None
Farrokh Hashem
Ladas & Parry LLP
Peugh Brian R.
LandOfFree
Method and device for masking ringing in a DDR SDRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and device for masking ringing in a DDR SDRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and device for masking ringing in a DDR SDRAM will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3667296