Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
2006-09-29
2008-12-23
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
C711S157000
Reexamination Certificate
active
07469365
ABSTRACT:
The writing address supply part210supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory220. The reading address supply part230alternately supplies to the operating memory220a plurality of addresses for reading a plurality of continuous bits corresponding to the header H from the operating memory220, and an address for reading 1 bit corresponding to the data D from the operating memory220, and reads the bit sequence such that the bits forming the bit sequence corresponding to the header H are scattered and arranged within the bit sequence forming the data D, from the operating memory. In accordance with such an interleaving device, it is possible to individually randomize frames according to their constituent data, and it is possible to transmit the bits that make up such data in a format which is most suited for said data.
REFERENCES:
patent: 4559625 (1985-12-01), Berlekamp et al.
patent: 5022029 (1991-06-01), Guichon
patent: 5255343 (1993-10-01), Su
patent: 5351246 (1994-09-01), Blaum et al.
patent: 5517511 (1996-05-01), Hardwick et al.
patent: 5572681 (1996-11-01), Nakamura et al.
patent: 5623504 (1997-04-01), Tolhuizen
patent: 5642365 (1997-06-01), Murakami et al.
patent: 5666370 (1997-09-01), Ganesan et al.
patent: 5729560 (1998-03-01), Hangenauer et al.
patent: 5751741 (1998-05-01), Voith et al.
patent: 5757822 (1998-05-01), Fisher et al.
patent: 5764649 (1998-06-01), Tong
patent: 5805469 (1998-09-01), Okamoto et al.
patent: 5862175 (1999-01-01), Sugiyama et al.
patent: 5898698 (1999-04-01), Bross
patent: 5907560 (1999-05-01), Spruyt
patent: 5946357 (1999-08-01), Sandin et al.
patent: 5978883 (1999-11-01), Hanna
patent: 6151690 (2000-11-01), Peeters
patent: 6154661 (2000-11-01), Goldburg
patent: 6192493 (2001-02-01), Combelles et al.
patent: 6282677 (2001-08-01), Inoue
patent: 6434718 (2002-08-01), Kawahara et al.
patent: 6826181 (2004-11-01), Higashida et al.
patent: 2007/0038902 (2007-02-01), Kawahara et al.
patent: 0 603 932 (1994-06-01), None
patent: 0 749 211 (1996-12-01), None
patent: 408097731 (1996-04-01), None
patent: 09-130269 (1997-05-01), None
patent: 09-161417 (1997-06-01), None
patent: 409331538 (1997-12-01), None
patent: WO 95/16311 (1995-06-01), None
patent: WO 96/27962 (1996-09-01), None
patent: WO97/08836 (1997-03-01), None
Office Action issued May 1, 2007 in the U.S. Appl. No. 11/540,059.
Sasaki, G. et al., “Scheduling Data Transfers in Preemptive Hierarchical Switching Systems with Applications to Packet Radio Networks”,One World Through Communications, May 4, 1992, IEEE vol. 2, Conf.11, pp. 691-700.
Frater, M. R. et al., “Wireless Video: The Impact of the Multiplexing Layer on Error Resilience”,First International Workshop on Wireless Image/Video Communications, Sep. 4, 1996, IEEE, pp. 20-25.
Chi, D., “A New Block Helical Interleaver”,Military Communications Conference, Oct. 11, 1992, IEEE, pp. 799-804.
EPO Office Action dated May 31, 2006.
English Translation of Makoto Yamamoto et al., “A Variety of Multiplexing Methods in Which Various Data is Combined and Transmitted,”Electronics Life, Jan. 1994, pp. 60-74 (18 pages).
Lim, Sung Ho et al. “Impact of Cell Unit Interleaving on Header Error Control Performance in Wireless ATM,” Global Telecommunications Conference, 1996. Globecom '96. Communications: The Key to Global Prosperity London, UK Nov. 18-22, 1996, New York, NY, USA,IEEE, US, Nov. 18, 1996, 1705-1709.
Tolstrup, Nielsen P. “Distributed Frame Synchronisation by Nonlinear-Shift-Register Sequences,”Electronics Letters, Feb. 22, 1973, vol. 9, No. 4, 73-75.
English abstract of JP 63-182977,Patent Abstracts of Japan, Jul. 28, 1988, vol. 0124, No. 57, one page.
A. J. van Wihngaarden et al. “Combinatorial Construction of High Rate Runlength-Limited Codes,” Global Telecommunications Conference, 1996. Globecom '96. Communications: The Key to Global Prosperity London, UK Nov. 18-22, 1996, New York, NY, USA,IEEE, US, Nov. 18, 1996, 343-347.
Makoto Yamamoto, et al., “Iroiro na jouhou o kasanete okuru tajuu houhou no iroiro”,Electronics Life, Jan. 1994, Nippon Housou Shuppan Kyoukai, pp. 60-74.
A.R. Calderbank and N. Seshadri. “Multilevel Codes for Uneaqual Error Protection”, Calderbank et al. IEEE Transactions on Information Theory, vol. 39, No. 4, pp. 1234-1248, Jul. 1993.
Hotani Sanae
Kawahara Toshiro
Miki Toshio
Suzuki Takashi
Brinks Hofer Gilson & Lione
Britt Cynthia
NTT Mobile Communications Network Inc.
LandOfFree
Method and device for interleaving and method and device for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and device for interleaving and method and device for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and device for interleaving and method and device for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4027684