Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-08
2004-04-27
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06727547
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to semiconductor devices, and particular LDMOS transistors, and defines a method and device for improving hot carrier reliability.
BACKGROUND OF THE INVENTION
In high voltage smart power (20-30V) applications, n-channel lateral DMOS (N-LDMOS) have commonly been used as driver transistors. Typically smart power management devices, as found in voltage converters, mobile phones, internet appliances, etc., combine high performance CMOS or bipolar transistors with a power MOS driver. As mentioned above, the power transistor commonly comprises an LDMOS device.
One of the problems created by the high drain voltages of the LDMOS drivers, however, is the potential for hot carrier degradation. In order to achieve high drive currents and minimal on-resistance LDMOS devices are often implemented in a checkerboard array of transistors, as shown in FIG.
1
. These comprise an array of transistors in which the drains
100
and sources
102
are connected by metal routing ties or connectors
104
, as shown, to define parallel sets of transistors that are controlled together to handle the high currents. A separate connection (not shown) is provided for the polysilicon gate, in order to control the resistance of the device. The effect of the array is to be able to handle high currents, reduce power dissipation, and provide for more uniform current flow per device area.
At high drain-source voltage (VDS) and high gate-source voltage (VGS), LDMOS devices, however, display destructive snapback due to the intrinsic parasitic NPN bipolar transistor. This raises hot carrier degradation concerns and limits the operating envelope and hot carrier (HC) stress bias condition to an electrically safe operating area (SOA).
One approach proposed by the present applicants in an earlier application, entitled “STRUCTURE AND METHOD FOR IMPROVING LDMOS TRANSISTOR HOT CARRIER RELIABILITY USING A DRAIN RING” to address hot carrier concerns, is to introduce a drain ring to redistribute internal array current flow. Simulations have shown that such a drain ring sinks more current than would be expected from geometric considerations, because of reduced current crowding at the drain ring. Furthermore the electric field is less at the edge of the array than at any of the center cells. This leads to less impact ionization at the drain edge and less on-resistance shift due to hot carrier degradation.
Nevertheless degradation due to hot carrier effects takes place over time due to the cumulative nature of hot carrier degradation. It is therefore desirable to find ways of further reducing hot carrier degradation.
SUMMARY OF THE INVENTION
The present invention provides a method and structure for reducing hot carrier degradation by providing a LDMOS array with a drain ring and providing the drain ring with a separate bias that is higher than that of the internal array drains.
According to the invention, there is provided a method of reducing hot-carrier degradation in a LDMOS array of at least one LDMOS transistor, each LDMOS transistor having an internal drain and source, comprising providing a drain ring for the array, and biasing the drain ring at a higher voltage than the at least one internal drain. Preferably the array includes a plurality of transistors with internal drains connected together and internal sources connected together. The drain ring may be biased at a voltage that is approximately 5V higher than the bias voltage on the internal drains.
Further, according to the invention, there is provided a method of adjusting the hot carrier degradation of a LDMOS device, comprising providing a drain ring that extends at least partly around the internal drain and source of the LDMOS device, and varying the voltage differential between the voltage to the internal drain of the LDMOS device and the voltage to the drain ring. Preferably the drain ring is biased at a higher voltage than the internal drain. The method may further comprise providing a plurality of LDMOS devices within the drain ring, wherein the internal drains are connected together and the internal sources are connected together.
Still further, according to the invention there is provided an array of LDMOS devices, with a drain ring extending at least partially around the LDMOS devices, wherein the drain ring is provided with a separate connection. Preferably a higher voltage is applied to the drain ring than to internal drains of the LDMOS devices of the array.
REFERENCES:
patent: 5910677 (1999-06-01), Irino
patent: 6169309 (2001-01-01), Teggatz et al.
Brisbin Douglas
Strachan Andy
Flynn Nathan J.
National Semiconductor Corporation
Quinto Kevin
Vollrath Jurgen
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