Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-01-23
2004-02-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C257S532000
Reexamination Certificate
active
06691294
ABSTRACT:
FIELD OF THE DISCLOSURE
The present invention relates generally to controlling ground bounce in semiconductor devices.
BACKGROUND
Ground bounce is known to occur in integrated circuits and to cause signal distortion and increased gate delays. Problems associated with ground bounce, or other power rail noise, become more pronounces as trace sizes are reduced for deep submicron technologies. The use of de-coupling capacitors has been proposed to address the problem of integrated circuit ground bounce. Discrete decoupling capacitors, which are external to an integrated circuit device, may not adequately resolve ground bounce introduced on an integrated circuit if the ground bounce is generated because of switching on the integrated device. Integrated decoupling capacitors, formed on the integrated circuit device, can be used to stop such internally generated ground bounce, but such internal capacitors can occupy significant die area.
Therefore, a method and or apparatus for controlling ground bounce that overcomes the problems of the prior art would be useful.
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Lee et al., “Simultaneously formed storage node contact and metal contact cell (SSMC) for 1 Gb DRAM and beyond” Electron Devices Meeting, 1996., International, Dec. 8-11, 1996.*
Weis et al., A highly cost efficient 8F2 DRAM cell with a double gate vertical transistor device for 100 nm and beyond Electron Devices Meeting, 2001. IEDM Technical Digest. International, Dec. 2-5, 2001 pp. 18.7.1-18.7.4.
ATI Technologies Inc.
Liu Andrea
Smith Matthew
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