Method and device for IC identification

Details Method and device for IC identification Method and device for IC identification

2005-04-19

2005-04-19

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C713S164000, C713S165000, C713S166000, C713S167000, C714S726000, C714S727000, C714S728000, C714S729000

Reexamination Certificate

active

06883151

ABSTRACT:
The present invention provides a method for IC identification. It can be used to identify the origin of the IC design, wherein said IC comprises at least a testing circuit for testing the functional correctness of said IC, and said testing circuit is activated by a testing activation signal. The testing circuit, after receiving a testing signal, will generate a testing result. The identification method comprises the steps of (1). providing an original identification data representing the origin of the IC; (2). transforming the original identification data into a digital identification data; (3). providing an identification circuit for generating the digital identification data, wherein the identification circuit is activated by the testing activation signal, and generates the digital identification data; (4). integrating the identification circuit and the testing circuit into a composite circuit, wherein the composite circuit will be activated by the testing activation signal, receive the testing signal, process the digital identification data from identification circuit and the testing result from the testing circuit, and generate an output signal; (5). inputting the testing activation signal and the testing signal to the composite circuit, and waiting for the output signal; (6). receiving the output signal and processing the output signal to obtain digital identification data; and (7). interpreting the digital identification data to obtain the original identification data.

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Lofstrom et al., “IC Identification Circuit Using Device Mismatch,” IEEE, Feb. 9, 2000, pp. 372-373.*
Quasem et al., “Benefits of a SoC-Specific Test Methodology,” IEEE, May-Jun. 2003, pp. 68-77.*
Kahng et al., “Constraint-Based Watermarking Techniques for Design IP Protection,” IEEE, Oct. 2001, pp. 1236-1252.*
Chapman et al., “IP Protection of DSP Algorithms for System on Chip Implementation,” IEEE, Mar. 2000, pp. 854-861.

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