Method and device for generating pseudo-random binary data

Electronic digital logic circuitry – Multifunctional or programmable – Sequential or with flip-flop

Reexamination Certificate

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C326S052000, C326S053000, C326S093000

Reexamination Certificate

active

07812636

ABSTRACT:
A device for generating k-bit parallel pseudo-random data includes “n” registers, from the first through the n-th registers (“n” is an integer not less than 3), and “k” exclusive-OR gates, from the first through the k-th exclusive-OR gates (“k” is an integer not less than 2). An output of the m-th register is input to the (m+k)th register (“m” is an integer between 1 and (n−k)). Outputs of the first through the (k−1)th exclusive-OR gates are respectively input to the second through the k-th exclusive-OR gates. An output of the first register is input to the first exclusive-OR gate. The outputs of the first through the k-th exclusive-OR gates are respectively input to the k-th through the first registers. Outputs of “k” registers, from the (n−k+1)th through the n-th registers are respectively input to the k-th through the first exclusive-OR gates, and also extracted as the k-bit parallel pseudo-random data.

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International Preliminary Report on Patentability and Written Opinion of the International Searching Authority dated Jan. 12, 2010, from the corresponding International Application.
International Search Report dated Jul. 31, 2007, from the corresponding International Application.

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