Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-12-28
2002-11-05
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S776000, C714S793000
Reexamination Certificate
active
06477678
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an error correcting coding method and apparatus for high bit rate digital data transmission, in particular long-haul fiber optic transmission, and to a corresponding decoding method and apparatus. The invention improves resistance to noise in transmitted digital messages by a system for coding the digital messages. It relates more particularly to the field of Forward Error Correction (FEC) coding, in which there is no feedback of information from the receiver, as opposed to Automatic Repeat reQuest (ARQ) coding, in which the receiver sends an acknowledgment. It is more particularly suitable for submarine fiber optic transmission systems.
In a very long-haul transmission system of this kind using a very high bit rate, in the order of several gigabits per second, FEC coding is essential to assuring quality of service and economizing on the number of optical amplifiers used as repeaters in the underwater part of the system. Error correcting coding reduces the overall cost of the system. It is also possible to regenerate the bits transmitted at reorganization nodes of a system of this kind. However, the complexity and the limited reliability of the equipment required to perform such regeneration rules out installing it in underwater repeaters.
Such links include the TAT12-TAT13 or Gemini transatlantic links, the SeaMeWe3 link running along the coasts of Europe and Asia and the Southern Cross or US/China transpacific links (some of these links are not yet operational).
More generally, in all transmission systems which use a very high bit rate, FEC coding has specific constraints in terms of the band expansion factor and above all in terms of processing speed and complexity. To enable implementation at low cost and with low power consumption it is therefore necessary to choose a coding process which offers high performance in terms of coding gain combined with low complexity.
The invention also envisages the use of concatenated coding. Concatenated coding generally uses an interior. code and an exterior code. Interior coding is the processing stage of the overall coding system which directly precedes transmission over the physical transmission medium, i.e. the optical fiber in this example. Exterior coding is the process coding the information bits to be transmitted before they are supplied to the. interior coding circuit. Concatenated coding achieves a good performance/complexity trade-off.
SUMMARY OF THE INVENTION
The object of the present invention is to propose several constructions and a low complexity implementation of interior coding, in particular in the context of a concatenated coding system. The concatenated coding then preferably uses a Reed-Solomon (RS) exterior code. The interior codes constructed in this way may nevertheless be usable on their own, depending on the intended application. Similarly, the exterior coding could use a code other than an RS code. For example, it could use a Convolutional Self-Orthogonal Code (CSOC). The object is to offer good performance and low complexity, highly suitable for transmission at very high bit rates, i.e. several gigabits per second, in particular in underwater fiber optic systems.
The prior art coding solutions include:
a) Non-binary Reed-Solomon block codes;
b) Binary Hamming or BCH block codes;
c) Concatenated codes using a) and/or b) for exterior and interior coding;
d) Concatenated coding of an PS code and a convolutional code with soft decision Viterbi decoding; and
e) “Turbo” coding.
The above coding solutions are insufficient, for the following reasons.
Solution a) uses very high performance coding and benefits from existing implementations of VLSI circuit components available from many silicon founders, thanks to the popularity of RS codes. For example there is the standard RS (255,239) code capable of correcting eight errors with only 16 (255-239) redundant bytes. However, RS codes using non-binary symbols are not suitable for binary transmission, e.g. fiber optic transmission. For example, for a fixed block length and fixed efficiency, a BCH code corrects a larger number of binary errors than an RS code.
With solution b) there is, in theory, no problem of adaptation to binary transmission. However, a Hamming code does not offer sufficient performance, although BCH codes necessitate the same complexity as RS codes. However, the drawback of BCH codes is that the circuits which execute them are not available for very high bit rates. Developing a BCH algebraic coding and decoding circuit is a much greater task than developing its RS counterpart. This is because there are no circuits for the BCH code in the libraries of VLSI circuit founders, although circuits are readily available for the RS code. There is therefore a considerable body of design work to be undertaken and the development time will be very long.
Solution c) means concatenated systems using an RS exterior code and another RS interior code or a BCH interior code. One of the two weaknesses of solutions a) and b) remains in this scheme. Moreover, this scheme can operate only with efficient interleaving, which can be very costly for high bit rates. This is because interior coding corrects most random errors but uncorrected residual errors tend to be grouped together. To correct them, the grouped residual errors must be distributed over several code words. This is achieved by interleaving on coding and corresponding de-interleaving on decoding.
Solution d) must use soft decisions if sufficient performance is to be achieved, i.e. with sampling and quantizing of the received signal over a dynamic range of several bits. There are still problems with implementing soft decision circuits for bit rates in the order of one gigabit per second. Viterbi decoding with a single decoder is not yet feasible. Several hundred decoders would be required for a decoder using Viterbi decoders in parallel, which is too great a number. Accordingly, the only circuit currently available is the ST-2060 from Standford Telecom, USA, which supports a bit rate of 45 Mbit/s. In the field of optical links, the bit rates envisaged are in the order of 10 Gbit/s per channel and it is planned to distribute 32 channels across the frequency bands used for optical transmission. Thus too great a number of Viterbi decoders (around 600) would be required. Also, interchanges between the various decoders would themselves be excessively voluminous and complex.
Solution e) requires soft decision decoding, quite apart from its inherent problem of complex iterative decoding. “Turbo” coding cannot be used for fiber optic transmission at several Gbits per second, for the same reasons as for solution d).
The object of the invention is to remedy the above drawbacks and to propose a solution capable of immediate and industrial implementation. The basic idea of the invention is to use convolutional self-orthogonal codes (CSOC) for the coding. The invention in fact uses composite convolutional self-orthogoral codes. CSOC are a class of codes with a high efficiency and very low complexity, but with low and medium coding gains. It is shown that they can nevertheless be beneficial in fiber optic transmission applications. They might also be beneficial in other applications.
The efficiency (K/N) is the ratio of the number (K) of information bits to be transmitted over the corresponding number (N) of symbols actually transmitted. The gain of a CSOC depends essentially on two parameters, namely the number of orthogonal equations (J) and the effective constraint length (Ne). Its gain expresses the reduction in the signal to noise ratio for which a given performance continues to be guaranteed. The greater the number of symbols to be sent, the greater the occupancy of the frequency bandwidth allocated to the channel, and the greater the redundancy.
The invention seeks not only low complexity but also to maximize gain. It will be shown that choosing CSOC circuits can nevertheless provide an extremely close match to the available bandwidth of the frequency channel u
Fang Juing
Lemaire Vincent
Alcatel
Baker Stephen M.
Sughrue & Mion, PLLC
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