Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-08-25
2003-10-21
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C713S503000
Reexamination Certificate
active
06636987
ABSTRACT:
BACKGROUND OF THE INVENTION
In the field of telecommunications it is known that the switching of signals in a digital network requires that there be a form of synchronization for all the nodes of the network. In order to accomplish the switching of digital signals in a network, the average rates of all the multiplex signals terminating on a switch in a node must be synchronized within some achievable bound, and the reference clock of the switch itself must be synchronized to the common rate of the incoming signals. Such a network is therefore typically considered as consisting of a traffic network and a synchronization network.
Synchronization networks are typically constructed by establishing a master-slave hierarchy of so-called stratum clocks, where each stratum corresponds to a different level of precision. For example, stratum
1
clocks are normally implemented with cesium beam technology of very high precision, whereas stratum
2
,
3
and
4
clocks have progressively lower accuracy. Synchronization references are passed from higher performance master clocks to equivalent or lower performance slave clocks. It is possible to supply more than one reference to a given slave clock, where this slave clock can then decide which reference to synchronize with.
FIG. 2
shows a schematic example of a clock system having a phase locked loop (PLL) structure. More specifically, a reference signal
1
is compared with the output
3
from a voltage controlled oscillator (VCO)
5
in a comparator
4
, and the comparator then outputs an appropriate VCO control value
2
(VCV) to the voltage controlled oscillator
5
.
In order to cope with variations in frequency between different nodes, digital switches typically incorporate so-called slip buffers, which are able to buffer the data frames if there is a difference between the write clock frequency and the read clock frequency. If the frequency difference continues for a sufficient amount of time, the slip buffer will eventually overflow or underflow, which results in a packet or frame of data either being repeated or deleted at the output of the buffer. Such slip events can have a different impact on the traffic network, depending on what kind of data is being transported. For example, when transporting digital data that employs automatic retransmission request (ARQ), a slip will result in requests for retransmission and thus degraded throughput.
PROBLEMS UNDERLYING THE INVENTION
When problems occur in the traffic network, such as e.g. a degraded throughput, it is important to be able to identify the cause of the problems. The problems can be caused by specific failures in the traffic network or the synchronization network. If failures occur in the synchronization network, due for example to the creation of timing loops, which will lead to a high slip rate, then the effects on the traffic network can appear far away from the root in the synchronization network, i.e. where the synchronization failure occurred. Due to this fact, it is possible that a network operator will undertake a wrong action at a wrong place.
It is therefore important to provide network operators with a means that can assist in finding out if the synchronization network is the real cause of problems appearing in the traffic network, and in which node of the network the synchronization is not working.
The known solution to this object is to check the quality of the synchronization references with test instruments, and on a higher level, to analyze the network synchronization plan. One problem with test instruments is that in case of a strong impact of the failure (as it could e.g. occur during the millennium shift), it would take a long time and large effort to simultaneously check the quality of all of the synchronization references in all of the network nodes. This is very time and cost consuming in case of failures in wide area networks (WAN). Moreover, the use of test instruments is only feasible if the network nodes do not branch strongly and if the synchronization network is simple and flat.
OBJECT OF THE PRESENT INVENTION
The object of the present invention is to provide a device and method for determining a synchronization fault that is applicable to any type of synchronization network, and is simple to implement.
SUMMARY OF THE PRESENT INVENTION
This object is solved by the subject-matter of the independent claims. Advantageous embodiments are described in the dependent claims.
In accordance with the present invention, the actual values of a clock control parameter (such as the VCO control value VCV in
FIG. 2
) are measured and compared with the predicted behavior of said clock control parameter. The predicted behavior is based upon a model that takes into account internal factors leading to a deviation between the reference clock and the internal clock (such as drift and temperature variations), such that a discrepancy between the predicted behavior and the measured values indicates a synchronization fault caused by the synchronization network.
Although the prediction model can be entirely based on theoretical considerations, it is preferable that the prediction model be based on the collection of significant data during a predetermined observation period that precedes the measurement period during which the predicted behavior is compared with the actual behavior. This collecting of data is done by observing the clock control value in the node or nodes e.g. under conditions when the synchronization network is either known to be failure-free or can be assumed to be failure-free. Then the characteristic values of the model are determined on the basis of the observed values, to thereby be able to make a prediction. Typically this prediction will consist in calculating a mask or value range inside of which the clock control parameter should lie at a given future point in time. Then, if the measured values lies outside of this mask or value range, it is judged that a synchronization fault is present.
The method of the present invention can be implemented in such a way that it is only triggered when a specific failure event occurs in the traffic network, to thereby be able to identify if this is due to a failure in the synchronization network, and if yes, in which nodes the synchronization failure has occurred, or the present invention can also be implemented to operate continuously to thereby be able to give an alarm or warning as soon as a synchronization failure occurs in any given node of the network.
The various aspects and advantages of the present invention shall become more apparent when studying the detailed embodiments, which shall be described in connection with the figures.
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