Method and device for data buffering

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

Reexamination Certificate

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Details

C710S022000, C710S056000, C711S170000

Reexamination Certificate

active

07581072

ABSTRACT:
A data buffer device that includes a write unit and a read unit, and is disposed between a first interface device and a second interface device is provided. The write unit further includes a first write buffer, a second write buffer and a write controller. The write controller controls the first write buffer and the second write buffer to receive and transmit data from the first interface device to the second interface device alternatively according to the requests of the first interface device and the second interface device. The read unit further includes a first read controller, a first read buffer and a second read buffer. The read controller controls the first read buffer and the second read buffer to receive and transmit data from the second interface device to the first interface device alternatively according to the requests of the first interface device and the second interface device.

REFERENCES:
patent: 5003463 (1991-03-01), Coyle et al.
patent: 5859846 (1999-01-01), Kim et al.
patent: 6279087 (2001-08-01), Melo et al.
patent: 6735667 (2004-05-01), Hashimoto et al.
patent: 6864861 (2005-03-01), Schehrer et al.
patent: 6882192 (2005-04-01), Gau
patent: 7035948 (2006-04-01), Liang et al.
patent: 1523134 (2005-04-01), None
patent: 546564 (2003-08-01), None
patent: 588252 (2004-05-01), None
patent: WO 0250655 (2002-06-01), None
TW office action mailed Jun. 12, 2007.

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