Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-06-28
2009-08-25
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C710S022000, C710S056000, C711S170000
Reexamination Certificate
active
07581072
ABSTRACT:
A data buffer device that includes a write unit and a read unit, and is disposed between a first interface device and a second interface device is provided. The write unit further includes a first write buffer, a second write buffer and a write controller. The write controller controls the first write buffer and the second write buffer to receive and transmit data from the first interface device to the second interface device alternatively according to the requests of the first interface device and the second interface device. The read unit further includes a first read controller, a first read buffer and a second read buffer. The read controller controls the first read buffer and the second read buffer to receive and transmit data from the second interface device to the first interface device alternatively according to the requests of the first interface device and the second interface device.
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TW office action mailed Jun. 12, 2007.
Hsu Jung-Tsan
Tsai Wen-Chung
Bataille Pierre-Michel
Thomas Kayden Horstemeyer & Risley
Via Technologies Inc.
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