Method and device for controlling internal power voltage,...

Details Method and device for controlling internal power voltage,... Method and device for controlling internal power voltage,...

2005-06-15

2008-10-14

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Powering

C365S233130

Reexamination Certificate

active

07436730

ABSTRACT:
In an embodiment, a device controls an internal power voltage in a semiconductor device. The device uses internal and external power voltages during a power-up period, and includes a power-up flag signal generator and a control circuit. The power-up flag signal generator generates a power-up flag signal based on the external power voltage. The control circuit provides a first internal power voltage to a peripheral circuit of the semiconductor device. During power-up the first internal power voltage varies according to a level of the external power voltage in response to the power-up flag signal having a first logic level. Accordingly, an internal power voltage may have a linear power-up slope during the power-up period and an initialization failure of any latch circuits in the peripheral circuit may be avoided. Also, power consumption of the latch circuits is reduced.

REFERENCES:
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patent: 6691248 (2004-02-01), Nishijima et al.
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patent: 10-0226221 (1999-07-01), None
patent: 2003-0009141 (2003-01-01), None
English language abstract of the Korean Publication No. 2003-0009141.

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