Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-12-26
2004-07-06
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S194000, C365S191000, C365S189070, C365S189050, C365S233100
Reexamination Certificate
active
06760263
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of Invention
The present invention generally relates to a method and device for controlling data, and more particularly, to a method and device for controlling data latch time.
2. Description of Related Art
The control circuit for reading the Synchronous Dynamic Random Access Memory (SDRAM) of the control chip in the currently used personal computer system can set the default Column Address Strobe Latency (abbreviated as CL) value. The function of the CL value is: when the memory control chip issues the memory read command, the control chip cannot receive the Data Strobe Signal (abbreviated as DQS) and the accurate memory data send from memory until a delay that equals CL times of the clock period. For example, if CL value equals 2, when memory issues the read command, the control chip cannot receive the data strobe signal (DQS) sent from memory until and memory data from memory after a delay of two times of the memory clock signal DCLK period.
Therefore, when the control chip intends to read the data in memory, it issues the memory read command first, then it receives the DQS signal sent from memory after a delay that equals CL times of the clock period. After the control chip receives the DQS signal, it delays the received DQS signal for a certain duration, after the delay, the control chip uses the delayed DQS signal to truly latch the Memory Data (abbreviated as MD) signal. In the Double Data Rate (abbreviated as DDR) memory, the memory data signal MD is latched based on the rising edge and the falling edge of the DQS signal. Wherein, the data strobe signal DQS comprises DQS[
8
:
0
], the memory data signal MD comprises MD[
71
:
0
]. Each DQS line corresponds to a byte of MD. For example, DQS
0
corresponds to MD[
7
:
0
].
The reason for using the delayed DQS signal to latch the MD signal mentioned above is mainly because the memory data signal MD and the data strobe signal DQS sent from memory are edge align. However, to read the data successfully, the data should be stable on the rising edge and the falling edge of the data strobe signal DQS, so the control chip has to delay the data strobe signal DQS for certain duration, so that the memory data can be ensured to be read correctly. However, no matter whether the delay time of the data strobe signal DQS is too much or too little, it results in the inaccurate reading of the memory data. Therefore, it is a very important matter to properly adjust the phase difference between the data strobe signal DQS and the memory data signal MD, that is to have the rising edge and the falling edge of the data strobe signal DQS fall into a stable area of MD, so that the memory data signal MD can be read accurately. Moreover, since the clock frequency of the currently used memory is getting higher now, when it suffers from the interference that results from the factors of the temperature variance or the voltage variance, it is easier to result in the inaccurate reading of the memory data that will cause risk of system halt. Therefore, how to conquer the inaccurate reading of the memory data that results from noise and to instantly adjust the proper delay time of the data strobe signal DQS has become a very important matter.
As shown in
FIG. 1
, the conventional method to read memory data latches the memory data signal MD by using a data strobe signal DQS that is delayed for a fixed duration equal to ¼ period of the memory clock signal DCLK. However, when the memory or the control chip suffers from the interference that results from the factors of the temperature variance or the voltage variance, this results in the offset of the memory data signal MD or the data strobe signal DQS that has just been read, thus causing the inaccurate latch of the memory data signal MD. The reason for this is the control chip cannot instantly adjust the delay time of the data strobe signal DQS, thus the memory data signal MD is not accurately latched. Moreover, if the conventional control chip has the capability to adjust the controlled delay time by using the controlled delay value, since the controlled delay value is set only once based on the default value by BIOS when the system initializes, after the system is turned on, when the system suffers from interference that results from the factors of the environment, element state, circuit layout, temperature or pressure the result is the inaccurate reading of the memory data. Since the control chip cannot instantly adjust the controlled delay time, the accuracy of the reading data cannot be improved. In summary, the prior art has following disadvantages:
1. The fixed controlled delay value equals to ¼ period of the memory clock can not be instantly adjusted, so the accuracy of the reading data cannot be improved.
2. The controlled delay value is set only once based on the default value by BIOS when the system initializes, so when the system suffers from interference that results from the factors of the environment, element state, circuit layout, temperature or pressure the result is the inaccurate reading of the memory data. Since the control chip cannot instantly adjust the controlled delay time, the accuracy of the reading data cannot be improved.
SUMMARY OF INVENTION
Therefore, the present invention provides a method and device for controlling data latch time. When the system suffers from the interference that results from the factors of temperature variance or voltage variance resulting in the offset of the memory data, the control chip of the present invention can instantly adjust the controlled delay value to ensure the accuracy of the read memory data.
In order to achieve the above and other objectives, the present invention provides a device for controlling the data latch time. The device comprises a delay value controller, a back edge data comparison circuit, a front edge data comparison circuit, and a state unit. Wherein, the delay value controller provides a controlled delay value. The back edge data comparison circuit receives a first data strobe signal and a first data signal, delays the first data strobe signal and sequentially latches the first data on the first data signal and performs comparison, according to respectively the controlled delay value and a value of a first offset added to the controlled delay value. The front edge data comparison circuit receives a second data strobe signal and a second data signal, delays the second data strobe signal and sequentially latches the second data on the second data signal and performs comparison, according to respectively the controlled delay value and a value of a second offset subtracted from the controlled delay value. The state unit receives a first comparison result of the front edge data comparison circuit and a second comparison result of the back edge data comparison circuit, provides the decision to the delay value controller for dynamically adjusting the controlled delay value.
The present invention further provides a method for controlling the data latch time, comprising the steps of: Providing a controlled delay time to delay a first data strobe signal for a duration equal to the controlled delay time and latching a first data on a first data line after the delay; delaying a second data strobe signal for a duration equal to the controlled delay time and latching a second data on a second data line after the delay. Providing a back edge controlled delay time to delay the data strobe signal for a duration equal to the back edge controlled delay time and latching a third data on the first data line after the delay, wherein the back edge controlled delay time is greater than the controlled delay time by a value equal to a first offset. Providing a front edge controlled delay time to delay the data strobe signal for a duration equal to the front edge controlled delay time and latching a fourth data on the second data line after the delay, wherein the front edge controlled delay time is less than the controlled delay time by a value equal to a second offset. Decre
Jiang Chyun IP Office
VIA Technologies Inc.
Yoha Connie C.
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