Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1999-10-01
2002-06-25
Kim, Matthew M. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S137000, C711S213000
Reexamination Certificate
active
06412059
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and device for controlling a cache memory and, particularly, to a method and device for controlling a cache memory, in such a way that an information such as instructions and/or data, etc., which is requested by a processor, is read out from a cache memory or a main memory and supplied to the processor.
2. Description of Related Art
FIG. 9
is a block circuit diagram showing an example of an electrical construction of a main portion of a data processor to which a conventional cache memory control device is applied.
The data processor shown in
FIG. 9
is constructed with, mainly, a processor
1
, a cache memory control device
2
and a main memory device
3
. The cache memory control device
2
is constructed with, mainly, a cache memory
4
, a tag memory
5
, an address generator circuit
6
, a comparator
7
, buffers
8
to
11
, an LRU (Least Recently Used) information generator circuit
12
and an LRU memory
13
.
The processor
1
performs a data processing by controlling various portions of the data processor. The cache memory control device
2
reads out an information such as instructions and/or data, etc., which is requested by the processor
1
, from the cache memory
4
or the main memory device
3
, as occasion demands, and supplies the information thus read out to the processor
1
. The information such as instructions and/or data, etc., which are necessary for the processor
1
to perform a data processing, is stored in the main memory device
3
.
The cache memory
4
temporarily stores the information such as instructions and/or data, etc., which is read out from the main memory device
3
. In order to search the information stored in the cache memory
4
, the tag memory
5
stores a tag, which is a portion of an address of the information. The address generator circuit
6
generates an address necessary to read the information, to which the processor
1
requests an access, from the main memory device
3
, in a case of “mishit”, that is, when the information is not stored in the cache memory
4
. The comparator
7
compares the tag which is a portion of the address supplied from the processor
1
with a plurality of tags read out from the tag memory
5
and outputs a hit information in a case of “hit”, that is, when the information requested by the processor
1
is stored in the cache memory
4
and a tag, which is the same as the tag, is found in the tags read out from the tag memory. The buffer
8
temporarily stores the address supplied from the processor
1
. The buffer
9
temporarily stores the hit information supplied from the comparator
7
. Buffer
10
temporarily stores the information read out from the cache memory
4
. The buffer
11
temporarily stores the address generated by the address generator circuit
6
. The buffers
8
to
11
are constructed with latches and flip-flops, etc., respectively. In order to effectively utilize the cache memory
4
, the LRU information generator circuit
12
generates, on the basis of the hit information read out from the buffer
9
, an LRU information indicating that an information among the information stored in the cache memory
4
, which is not used for the longest time, is replaced by an information newly read out from the main memory device
3
. The LRU information is stored in an address of the LRU memory
13
, which address is read out from the buffer
8
.
An operation of the cache memory control device constructed as mentioned above will be described. First, when the processor
1
requests an access to a certain information and supplies a certain address to the cache memory control device
2
, the address is temporarily stored in the buffer
8
. The same address is also supplied to the cache memory
4
and the tag memory
5
. Therefore, a tag corresponding to the address is read out from the tag memory
5
. The comparator
7
compares the tag corresponding to a portion of the address supplied from the processor
1
with a plurality of tags read out from the tag memory a and outputs a hit information in a case of “hit”, that is, when the information requested by the processor
1
is stored in the cache memory
4
and a tag, which is the same as the tag corresponding to the portion of the address from the processor, is found in the tags read out from the tag memory. The buffer
9
temporarily stores the hit information supplied from the comparator
7
. Simultaneously with this processing, an information corresponding to the address is read out from the cache memory
4
when it is hit and is temporarily stored in the buffer
10
. The above mentioned processing up to the temporary storage of the information in the buffer
10
will be referred to as “first processing”.
Then, the LRU information generator circuit
12
generates the LRU information on the basis of the hit information read out from the buffer
9
and the LRU information is stored in the address in the LRU memory
13
, which is read out from the buffer
8
. In the case of hit, the information temporarily stored in the buffer
10
is supplied to the processor
1
. This processing will be referred to as “second processing”.
The above mentioned first and second processing are executed in pipe-line.
On the other hand, in the case of mishit, the address generator
6
generates an address for reading an information corresponding to the address from the main memory device
3
and the this generated address is temporarily stored in the buffer
11
. Therefore, the address temporarily stored in the buffer
11
is read out and supplied to the main memory device
3
. Thus, the information corresponding to the address supplied from the main memory device
3
is read out and stored in the cache memory
4
. Subsequently, the first processing and the second processing are executed.
When an address corresponding to an access request related to a certain information is supplied from the processor
1
in the conventional cache memory control device
2
mentioned above, it takes a time corresponding to at least one clock from the supply of the address An (n=1, 2, 3, . . . ) up to a time at which a search for a tag corresponding to the address in the tag memory
5
ends (see FIG.
10
(
1
)). Therefore, in the case of hit, it takes a time corresponding to at least 1 clock to read out the requested information Dn (n=1, 2, 3, . . . ) from the cache memory
4
(see FIG.
10
(
2
)). Thus, there is a defect that it is impossible to immediately respond to an access request from the processor
1
, even when the information is stored in the cache memory
4
.
Further, when there are successive hits in the described conventional cache memory control device
2
, the cache memory
4
, the tag memory
5
and the LRU memory
13
are always accessed with considerable power consumption since the reading of the information (see FIG.
10
(
2
)), the reading of the tag (see FIG.
10
(
3
)) and the update of the LRU information (see FIG.
10
(
4
)) are executed in pipe line processing. Therefore, when the processor
1
and the cache memory control device
2
are constructed as a single IC chip, operating temperature of the IC chip is increased, causing the life thereof to be shortened. In order to solve this problem, a heat radiator or a fan has to be provided, resulting in another defect that the data processing device becomes high in cost and large in size.
SUMMARY OF THE INVENTION
The present invention was made in view of the above mentioned state of art and an object of the present invention is to provide a method and device for controlling a cache memory, with which a quick response to an access request from a processor is realized with reduced power consumption.
In order to achieve the above object, a cache memory control method according to a first aspect of the present invention, which is used in a cache memory control device including a cache memory storing an information, a tag memory storing tags constructing addresses corresponding to the information stored in the ca
Elmore Stephen
Kim Matthew M.
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