Method and device for configuration of PLDs

Details Method and device for configuration of PLDs Method and device for configuration of PLDs

2007-01-02

2007-01-02

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S040000, C326S046000

Reexamination Certificate

active

10954981

ABSTRACT:
A Programmable Logic Device provides efficient scalability for configuration memory programming while requiring reduced area for implementation. The device includes an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.

REFERENCES:
patent: 6972791 (2005-12-01), Yomeyama
patent: 2004/0015758 (2004-01-01), Pathak et al.

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