Method and device for characterizing a CMOS logic cell to be...

Details Method and device for characterizing a CMOS logic cell to be... Method and device for characterizing a CMOS logic cell to be...

2005-03-22

2005-03-22

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S013000, C703S014000, C703S015000, C327S051000, C327S536000

Reexamination Certificate

active

06871330

ABSTRACT:
A method for characterizing a CMOS logic cell of the partially depleted silicon-on-insulator type (PD-SOI) may include modeling the logic cell and determining internal potentials of transistors of the cell in a dynamic equilibrium state based upon a functional simulation of the modeled cell. This may be done using a binary stimulation signal having an initial logic value. The dynamic equilibrium state may be based upon a cancellation, to within a precision error, of the sum of the squares of variations in the quantities of charge in floating substrates of the transistors taken over a period of two successive transitions of the stimulation signal.

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