Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-05-08
2000-04-18
Dinh, Son T.
Static information storage and retrieval
Floating gate
Particular biasing
36518518, 36518522, 36518529, G11C 1604
Patent
active
060523069
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a method by which, in an electrically erasable and programmable read-only semiconductor memory, unambiguous programming and unambiguous erasure are possible and are largely independent of technology-dictated fluctuations in the dependence of the threshold voltage on the high voltage.
DESCRIPTION OF THE PRIOR ART
In the case of MOS field-effect transistors, doping regions are present in a substrate on both sides of a gate electrode which is arranged in an insulated manner over the substrate. Such doping regions are referred to as source and drain regions. By applying a voltage between the gate electrode and the substrate, in the case of an enhancement-mode field-effect transistor, for example, charge carriers from the substrate are concentrated under the gate electrode. By applying a voltage between the drain region and the source region, further charge carriers from the source region are injected into this enhanced region. A conductive channel is thereby formed under the gate electrode between the source region and the drain region wherein the conductivity of the channel can be controlled by the voltage across the gate electrode.
However, in order to form a conductive channel, a voltage must be applied between the gate electrode and the substrate, the voltage also must have a specific, technology-dependent minimum value, which is referred to as the threshold voltage.
In principle, electrically erasable read-only memory cells of the EEPROM or flash type have the same structure as MOS field-effect transistors, but they also have a further electrode which is completely surrounded by non-conductive material--that is to say is completely insulated. This additional electrode is referred to as a floating gate, between their gate electrode, or control electrode, and the substrate. The threshold voltage of the transistor forming a memory cell can be altered by applying a charge to this floating gate.
The application of charges to the floating gate is referred to as programming and the removal of the charges is referred to as erasure of the memory cell. Normally, the effect of programming is to shift the threshold voltage towards lower values wherein the transistor forming the cell is usually in the on state even without the application of a voltage to the control electrode.
In order to ascertain whether or not a cell is programmed, that is whether a logic "1" or "0" has been written to it, a voltage read voltage, is applied to the control electrode. This voltage lies approximately between the threshold voltages of a programmed cell and of an erased cell. The logic state of the cell can be ascertained depending on whether a current flows through the cell.
An EEPROM or flash cell is programmed or erased by a tunnelling current flowing from the substrate to the floating gate or vice versa. For this purpose, sufficient energy must be supplied to the charge carriers, which is done by applying a high voltage of approximately 15 V between the control electrode and the substrate and by forming an extremely thin insulating layer between the floating gate and the substrate. As result, a very high field strength occurs there.
To programme an n-channel transistor, positive charge carriers are applied to the floating gate which means when using a conventional positive high voltage, that the latter must be applied to the drain region while 0 V are applied to the control electrode. Correspondingly, in order to erase the cell, the high voltage is then applied to the control electrode and 0 V is applied to the drain region. This then removes the charge carriers again from the floating gate.
A specific minimum high voltage is fundamentally necessary in order to allow the tunnelling current to begin. However, the degree of programming or erasure also depends on the actual level of the high voltage and on the period of time during which it is applied. The fundamental profile of the threshold voltage Uth, and hence of the charge state of the floating gate, as a function of the
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patent: 5508958 (1996-04-01), Fazio et al.
patent: 5544117 (1996-08-01), Nakayama et al.
patent: 5883833 (1999-03-01), Naura et al.
patent: 5909390 (1999-06-01), Harari
Patents Abstracts of Japan
Sedlak Holger
Viehmann Hans-Heinrich
Dinh Son T.
Siemens Aktiengesellschaft
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