Method and device for automated layer generation for...

Details Method and device for automated layer generation for... Method and device for automated layer generation for...

2008-01-01

2008-01-01

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07315994

ABSTRACT:
In a FinFET integrated circuit design, a combined cell structure contains two single cell structures at a first design hierarchy having fin shapes, the cell structures are placed adjacent to each other. The combined fin shapes of the two single cell structures at the first design hierarchy lead to a violation of a design rule related to fin topology in the overlapping region. A fin generation tool thus decides not to place the fins in the first design hierarchy. The fin generation is delegated another design hierarchy resulting in the generation of a single combined fin for both single cells.

REFERENCES:
patent: 5414636 (1995-05-01), Ema
patent: 6413802 (2002-07-01), Hu et al.
patent: 6662350 (2003-12-01), Fried et al.
patent: 7013447 (2006-03-01), Mathew et al.
patent: 7187046 (2007-03-01), Wu et al.
“FinFET Technology for Future Microprocessors”, T. Ludwig et al., 2003 IEEE International SOI Conference, Newport Beach, CA, pp. 33-34, ISBN 0-7803-7815-6.

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