Method and device for adjusting lane ordering of peripheral...

Details Method and device for adjusting lane ordering of peripheral... Method and device for adjusting lane ordering of peripheral...

2007-02-06

2007-02-06

Perveen, Rehana (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S107000, C710S317000

Reexamination Certificate

active

10921116

ABSTRACT:
A method for adjusting the PCI Express lane ordering is disclosed, comprising the following steps. The first packet associated with a first PCI Express lane ordering is sent to the peripheral device. The peripheral device replies the second packet associated with the second PCI Express lane ordering. Whether the PCI Express lane ordering is correct is determined in response to said second packet. The first PCI Express lane ordering is adjusted while the first PCI Express lane ordering does not match the second PCI Express lane ordering. Preferably, the adjusted PCI Express lane order matches the normal order or the reverse order. Then, reset and reinitialize the peripheral device. The resetting step can be accomplished by sending reset packets, or changing the common mode voltage level in order to reset the bridge chipset of the PC.

REFERENCES:
patent: 5446482 (1995-08-01), Van Aken et al.
patent: 5828853 (1998-10-01), Regal
patent: 6424347 (2002-07-01), Kwon
patent: 6961347 (2005-11-01), Bunton et al.
patent: 2004/0088469 (2004-05-01), Levy
patent: 2005/0259696 (2005-11-01), Steinman et al.
PCI Express Base Specification Revision 1.0—Apr. 29, 2002—Section 4—pp. 1-2, 149-214.

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