Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-07-13
2003-12-16
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06665846
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
During the realization of large scale integrated circuits, it is customary first to create a circuit design specifying what components are provided and what switching behavior the integrated circuit is intended to have. Proceeding from this circuit design, a layout is created which describes the geometrical form and arrangement of all components in the circuit arrangement. The components include, in particular, doped regions, insulating structures, conductive structures, metalization planes, contacts, etc. The layout is generally created with the aid of a computer and can be present both as a file and as a plan. The layout is the basis used to create mask sets which are subsequently used in the technological fabrication of the integrated circuit.
Due to inaccuracies, design errors and compromises, for instance in the case of minimum dimensions, during the creation of the layout, it is possible that the circuit fabricated according to a layout will have different properties than demanded in the circuit design. In order to ensure that the fabricated circuit functions according to the circuit design as exactly as possible, the layout is frequently subjected to a verification method before a mask set is fabricated which is based on the verified layout. The verification involves examining whether the structures of the integrated circuit which are provided according to the layout actually have the electrical properties specified in the circuit design.
Since the switching speed of integrated circuits is considerably dependent on the interconnection capacitances occurring in the circuit, capacitance calculations are carried out in the course of verification. To that end, interconnection networks, often also called networks, are considered. An interconnection network is understood to be a conductive path within the large scale integrated circuit. The path may be branched and may extend over the entire area of the integrated circuit. Different interconnection networks are insulated from one another. During the capacitance calculation, it is necessary to determine the capacitance between these networks. For high-precision calculations in the deep submicron range, this can be carried out only by programs, so-called field solvers, in which the three-dimensional Laplace equation is solved numerically. In the case of large integrated circuits having a chip area of a few cm
2
, however, this Laplace equation cannot be handled as a whole by computers available today, for complexity reasons. Therefore, it is customary, during the capacitance calculation, to define partitioning cells for which the three-dimensional Laplace equation can be solved numerically.
It has been proposed (see, for example, Z. Zhu et al., IEEE Transaction on Microwave Theory and Techniques Vol. 45, No. 8, August 1977, pp. 1179 to 1184, Z. Zhu et al., Vol. 46, No. 8, August 1998, pp. 1037 to 1044, E. A. Dengi et al. in proceeding of DAC 1997, pp. 1 to 6 and A. H. Zemanian et al., IEEE Transaction on Computer-Aided Design Vol 8, No. 12, December 1989, pp. 1319 to 1326), for the purpose of dealing with this problem, to carry out a “so-called domain decomposition”, in which the partitioning cells are determined by electrostatic boundary conditions of all the interconnection networks. To date, however, this procedure has been expounded in the literature only using relatively small large-scale-integrated circuits, the chip area having been limited to a maximum of 200 &mgr;M
2
, since the determination of these electrostatic boundary conditions of all the interconnection networks is complex.
Furthermore, it has been proposed (see, for example, Y. L. Le Coz et al., Solid State Electronics, Vol. 35, No. 7, pp. 1005 to 1012, 1992) to solve the Laplace equation stochastically. However, statistical errors occur in this case. Furthermore, the calculation of coupling portions between different interconnection networks, with the same run time, is possible only in a relatively inaccurate manner. Finally, this method is limited to structures with angles of 45° and 90°.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method a configuration for using a computer to verify the layout for fabricating a large scale integrated circuit which overcomes the above-mentioned disadvantageous of the prior art methods and configurations of this general type. In particular, it is an object of the invention to provide such a method that can be carried out with tenable computation complexity even in the case of integrated circuits having chip areas of a few cm
2
.
With the foregoing and other objects in view there is provided, in accordance with the invention a method for verifying a layout of an integrated circuit, which includes: providing a layout containing a plurality of interconnection networks. One of the plurality of the interconnection networks that are contained in the layout is selected to thereby obtain a selected interconnection network. The selected interconnection network has dimensions. The method includes calculating a capacitance of the selected interconnection network with respect to others of the plurality of the interconnection networks that are contained in the layout. The capacitance is calculated by performing the following steps: determining a filter polygon that surrounds the dimensions of the selected interconnection network; providing the filter polygon with dimensions that are enlarged by a predetermined extent relative to the dimensions of the selected interconnection network; determining portions of others of the plurality of the interconnection networks that overlap the filter polygon; and determining a capacitance between the selected interconnection network and the portions of the others of the interconnection networks that overlap the filter polygon.
In order to verify a layout, an interconnection network contained in the layout is selected. The interconnection network is a continuous structure including conductive elements, such as doped semiconductor regions, doped polycrystalline semiconductor layers, metal layers and the like, which can be arranged in different planes and which touch or overlap one another. The interconnection network may also contain conductive parts of a component. An interconnection network thus constitutes a continuous conductive connection in the integrated circuit. For the selected interconnection network, the capacitance with respect to the other interconnection networks contained in the layout is calculated as follows: a filter polygon is determined, whose form corresponds to the form of the selected interconnection network. The dimensions of the filter polygon is enlarged by a predeterminable extent relative to the dimensions of the selected interconnection network. The filter polygon is thus a geometrical area produced by enlarging the geometrical area of the selected interconnection network by the predeterminable extent.
Afterward, the portions of all the interconnection networks which overlap the filter polygon are determined. These portions may be arranged in the region of the filter polygon both in the same plane as the selected interconnection network and in planes lying above or below it. The capacitance between the selected interconnection network and the portions of the other interconnection networks which overlap the filter polygon is calculated. Portions of the other interconnection networks which are arranged outside the filter polygon are not taken into account during the capacitance calculation. This method exploits the fact that the contribution to the capacitance decreases with the distance between conductive structures. In the method, the contributions which are still to be taken into account during the capacitance calculations are controlled by way of the predeterminable extent.
Since, in the method, only the selected interconnection network is considered as a whole and only the capacitances between the selected interconnection network and the portions of the other interconnection networks
Frerichs Martin
Rein Achim
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Rossoshek Helen B
Siek Vuthe
LandOfFree
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