Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2000-02-02
2004-11-16
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S022000, C712S244000
Reexamination Certificate
active
06820190
ABSTRACT:
I. FIELD
The present invention relates to digital computer systems, and more particularly but not by way of limitation, to methods and an apparatus for processing instructions in such systems.
II. BACKGROUND
Microprocessors exist that implement a reduced instruction set computing (RISC) instruction set architecture (ISA) and an independent complex instruction set computing (CISC) ISA by emulating the CISC instructions with instructions native to the RISC instruction set. Instructions from the CISC ISA are called “macroinstructions.” Instructions from the RISC ISA are called “microinstructions.”
Streaming Single-Instruction Multiple-Data Extensions (SSEs) have been developed to enhance the instruction set of the latest generation of certain computer architectures, for example the IA-32 architecture. The SSEs include a new set of registers, new floating point data types, and new instructions. Specifically, the SSEs comprise eight 128-bit Single-Instruction Multiple-Data (SIMD) floating point registers (XMM0 through XMM7) that can be used to perform calculations and operations on floating point data. These XMM registers are shown in FIG.
1
A. Each 128-bit floating point register contains four packed 32-bit single precision (SP) floating point (FP) numbers. The structure of the packed 32-bit SP FP numbers is illustrated in the example of
FIG. 1B
, where four 32-bit SP FP numbers (numbered
0
through
3
) are shown as if stored in the XMM2 SSE register. In architectures designed to support the SSEs, such as its native architecture, a single instruction of the SSE instruction set operates in parallel on the four 32-bit SP FP numbers in a particular XMM register.
The SSEs also include a status and control register called the MXCSR register. The format of the MXCSR is illustrated in the example of FIG.
1
C. The MXCSR register may be used to selectively mask or unmask exceptions. Specifically, bits
7
-
12
of the MXCSR register may be used by a programmer to selectively mask or unmask a particular exception. Masked exceptions are those exceptions that a programmer wishes to be handled automatically by the processor which may provide a default response. Unmasked exceptions, on the other hand, are those exceptions that the programmer wishes to be handled by invocation of an interrupt or an operating system handler. This invocation of the handler transfers control of the operating system (such as Windows by Microsoft) where the problem may be corrected or the program terminated.
The MXCSR register may also be used to keep track of the status of exception flags. Bits
0
-
5
of the MXCSR register indicate whether any of six exceptions have occurred in the execution of an SSE instruction. Those exceptions include the following: invalid operation (I), divide-by-zero (Z), denormal operation (D), numeric overflow (O), numeric underflow (U), or inexact result (P). The status of the flags are “sticky,” meaning that once they art, set, they are not cleared by any subsequent SSE instruction, even if one is performed without exception. The status flags can only be cleared by a special instruction, usually issued from the operating system.
The exception flags of
FIG. 1C
are the result of a bitwise logical-OR operation on all four of the 32-bit SP FP operations that are performed on a particular 128-bit register XMM register. (One operation on each of the four 32-bit SP FP numbers.) Thus, if an exception occurs as to any one of the four 32-bit SP FP numbers, the exception flag for that particular type of exception will be raised, indicating some type of problem has occurred in the system. The invalid operation (I) divide by zero (Z), and denormal operation (D) exceptions are pre-computation exceptions, meaning that they are detected before any arithmetic or logical operations occur. That is, they can be detected without doing any computations. The other three exceptions, numeric overflow (O), numeric underflow (U), and inexact result (P) are post-computation exceptions, meaning that they are detected after the operations have been performed. It is possible for an operation performed on a sub-operand (i.e., one of the four operands in a 128-bit XMM register) to raise multiple flags.
SSEs have the following rules for exceptions:
1. When an unmasked exception occurs, the processor executing the instruction will not change the contents of the XMM register. In other words, results will not be committed or stored until it is known that no unmasked exceptions have occurred with respect to any of the four 32-bit SP FP numbers.
2. If there is a masked exception, all exception flags are updated.
3. In the case of unmasked pre-computation exceptions, all flags relating to pre-computation exceptions, whether masked or unmasked, will be updated. However, no subsequent computations are permitted, meaning that no post-execution exceptions can or will occur. This, of course, means that no post-execution exception flags will change or be updated.
4. In the case of unmasked post-computation exceptions, all post-execution conditions, whether masked or unmasked, will be updated, as will 41 pre-computation exceptions. Any pre-computation exceptions will be masked exceptions only because, if the pre-computation exception was unmasked, under Rule No. 3 above, no further computations would have been permitted.
Further information regarding streaming SIMD extensions may be found in the
Intel Architecture Software Developer's Manual
, (1999), Volumes 1 through 3, Intel Order Numbers 243190, 243191, 243192, which are hereby incorporated by reference.
In many architectures, provisions have not been made for the SSE instructions. In these non-native architectures, the eight 128-bit floating point XMM registers capable of containing four 32-bit SP FP numbers are not available. In some non-native architectures, the eight 128-bit XMM registers may be mapped onto 16 floating point registers (e.g., IA-64 registers) that may be less than 128 bits and more than 64 bits wide. Specifically, some architectures use 82-bit registers to hold two 32-bit SP FP numbers (the bits in excess, of 64 may be used for the special encoding used to indicate the register holes SIMD-type 32-bit SP FP numbers). An example is shown in FIG.
1
D. Note that the four 32-bit SP FP numbers
0
-
3
stored in the XMM2 register of the SSE native environment (
FIG. 1B
) are now stored in two 82-bit registers, XMM2_Low and XMM2_High, containing the “low half of the XMM2 register” and the “high half of the XMM2 register,” respectively. This makes parallel execution of an operation on each of the four 32-bit SP FP numbers difficult.
Thus, in this non-native environment, the SSE instructions must be executed by emulation. Specifically, operations may first be performed on two of the four 32-bit SP FP numbers (in parallel) and then be performed on the remaining two 32-bit SP FP numbers (again, in parallel). Operations may alternatively be performed on only one or at least three of the 32-bit SP FP numbers. For example, an operation may be performed on the operands in the low half, XMM2_low, and then on the high half, XMM2_High. However, given the SSE rules for handling exceptions and updating exception flags, problems arise when emulating SSE instructions in this partially parallel, partially sequential manner. For example, consider a set of instructions being performed on the low half and high half of FIG.
1
D:
XMM2:=OP(XMM3, XMM4)
emulated by
XMM2_Low:=OP(XMM3_Low, XMM4_Low)
XMM2_High:=OP(XMM3_High, XMM4_High)
Assume that the first instruction is executed without an unmasked exception as to the operands in the low halves, XMM3_Low and XMM4_Low. The results of this operation are then properly committed in XMM2_Low. Assume now that execution of the second instruction on the high halves results in a pre-computation unmasked exception. According to the SSE rules, no subsequent operations are then to be performed on any of the four 32-bit SP FP numbers because of that pre-computation unmasked exception. But here, however results of the op
Knebel Patrick
Safford Kevin David
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