Method and computer program product for estimating wire loads

Details Method and computer program product for estimating wire loads Method and computer program product for estimating wire loads

2005-11-15

2005-11-15

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06966045

ABSTRACT:
A wire load estimating method comprises (1) reading a netlist; (2) generating connection information including the names of signals, the identification names and the names of pins of instances which include cells, macro blocks and synthesized blocks as described in the netlist; (3) dividing an area of a chip into two or more regions and determining connection point coordinates for each of the regions by the use of the connection information and locations of the instances as placed; (4) determining a wiring path by the use of the connection point coordinates; and (5) estimating a wire capacitance value and a wire resistance value with reference to the wiring path.

REFERENCES:
patent: 5790841 (1998-08-01), Scherer et al.
patent: 5987086 (1999-11-01), Raman et al.
patent: 6266803 (2001-07-01), Scherer et al.
patent: 6510542 (2003-01-01), Kojima
patent: HEI 07-105240 (1995-04-01), None

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